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Apply SBI/CBI/TEST in HAL

Scott Lahteine 4 年之前
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01825d883e

+ 1
- 1
Marlin/src/HAL/LPC1768/main.cpp 查看文件

@@ -117,7 +117,7 @@ void HAL_init() {
117 117
     PinCfg.Pinmode = 2;    // no pull-up/pull-down
118 118
     PINSEL_ConfigPin(&PinCfg);
119 119
     // now set CLKOUT_EN bit
120
-    LPC_SC->CLKOUTCFG |= (1<<8);
120
+    SBI(LPC_SC->CLKOUTCFG, 8);
121 121
   #endif
122 122
 
123 123
   USB_Init();                               // USB Initialization

+ 2
- 2
Marlin/src/HAL/STM32/HAL_MinSerial.cpp 查看文件

@@ -71,8 +71,8 @@ static void TXBegin() {
71 71
       volatile uint32_t ICER[32];
72 72
     };
73 73
 
74
-    NVICMin * nvicBase = (NVICMin*)0xE000E100;
75
-    nvicBase->ICER[nvicIndex / 32] |= _BV32(nvicIndex % 32);
74
+    NVICMin *nvicBase = (NVICMin*)0xE000E100;
75
+    SBI32(nvicBase->ICER[nvicIndex >> 5], nvicIndex & 0x1F);
76 76
 
77 77
     // We NEED memory barriers to ensure Interrupts are actually disabled!
78 78
     // ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )

+ 11
- 14
Marlin/src/HAL/STM32/tft/tft_ltdc.cpp 查看文件

@@ -45,7 +45,6 @@
45 45
 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
46 46
 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
47 47
 
48
-
49 48
 void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command) {
50 49
 
51 50
   __IO uint32_t tmpmrd =0;
@@ -192,7 +191,7 @@ void LTDC_Config() {
192 191
 
193 192
   hltdc_F.Instance = LTDC;
194 193
 
195
-/* Layer0 Configuration ------------------------------------------------------*/
194
+  /* Layer0 Configuration ------------------------------------------------------*/
196 195
 
197 196
   /* Windowing configuration */
198 197
   pLayerCfg.WindowX0 = 0;
@@ -289,22 +288,21 @@ void TFT_LTDC::DrawRect(uint16_t sx, uint16_t sy, uint16_t ex, uint16_t ey, uint
289 288
   uint16_t offline = TFT_WIDTH - (ex - sx);
290 289
   uint32_t addr = (uint32_t)&framebuffer[(TFT_WIDTH * sy) + sx];
291 290
 
292
-  DMA2D->CR &= ~(1 << 0);
291
+  CBI(DMA2D->CR, 0);
293 292
   DMA2D->CR = 3 << 16;
294 293
   DMA2D->OPFCCR = 0X02;
295 294
   DMA2D->OOR = offline;
296 295
   DMA2D->OMAR = addr;
297 296
   DMA2D->NLR = (ey - sy) | ((ex - sx) << 16);
298 297
   DMA2D->OCOLR = color;
299
-  DMA2D->CR |= 1<<0;
298
+  SBI(DMA2D->CR, 0);
300 299
 
301 300
   uint32_t timeout = 0;
302
-  while((DMA2D->ISR & (1<<1)) == 0)
303
-  {
301
+  while (!TEST(DMA2D->ISR, 1)) {
304 302
     timeout++;
305
-    if(timeout>0X1FFFFF)break;
303
+    if (timeout > 0x1FFFFF) break;
306 304
   }
307
-  DMA2D->IFCR |= 1<<1;
305
+  SBI(DMA2D->IFCR, 1);
308 306
 }
309 307
 
310 308
 void TFT_LTDC::DrawImage(uint16_t sx, uint16_t sy, uint16_t ex, uint16_t ey, uint16_t *colors) {
@@ -314,7 +312,7 @@ void TFT_LTDC::DrawImage(uint16_t sx, uint16_t sy, uint16_t ex, uint16_t ey, uin
314 312
   uint16_t offline = TFT_WIDTH - (ex - sx);
315 313
   uint32_t addr = (uint32_t)&framebuffer[(TFT_WIDTH * sy) + sx];
316 314
 
317
-  DMA2D->CR &= ~(1 << 0);
315
+  CBI(DMA2D->CR, 0)
318 316
   DMA2D->CR = 0 << 16;
319 317
   DMA2D->FGPFCCR = 0X02;
320 318
   DMA2D->FGOR = 0;
@@ -322,15 +320,14 @@ void TFT_LTDC::DrawImage(uint16_t sx, uint16_t sy, uint16_t ex, uint16_t ey, uin
322 320
   DMA2D->FGMAR = (uint32_t)colors;
323 321
   DMA2D->OMAR = addr;
324 322
   DMA2D->NLR = (ey - sy) | ((ex - sx) << 16);
325
-  DMA2D->CR |= 1<<0;
323
+  SBI(DMA2D->CR, 0);
326 324
 
327 325
   uint32_t timeout = 0;
328
-  while((DMA2D->ISR & (1<<1)) == 0)
329
-  {
326
+  while (!TEST(DMA2D->ISR, 1)) {
330 327
     timeout++;
331
-    if(timeout>0X1FFFFF)break;
328
+    if (timeout > 0x1FFFFF) break;
332 329
   }
333
-  DMA2D->IFCR |= 1<<1;
330
+  SBI(DMA2D->IFCR, 1);
334 331
 }
335 332
 
336 333
 void TFT_LTDC::WriteData(uint16_t data) {

+ 1
- 1
Marlin/src/HAL/STM32F1/HAL_MinSerial.cpp 查看文件

@@ -55,7 +55,7 @@ static void TXBegin() {
55 55
     nvic_irq_disable(dev->irq_num);
56 56
 
57 57
     // Use this if removing libmaple
58
-    //NVIC_BASE->ICER[1] |= _BV(irq - 32);
58
+    //SBI(NVIC_BASE->ICER[1], irq - 32);
59 59
 
60 60
     // We NEED memory barriers to ensure Interrupts are actually disabled!
61 61
     // ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )

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