|
@@ -86,7 +86,6 @@
|
86
|
86
|
#define ST7565_DELAY_3 CPU_ST7565_DELAY_3
|
87
|
87
|
#endif
|
88
|
88
|
|
89
|
|
-
|
90
|
89
|
#if ENABLED(SHARED_SPI) // Re-ARM requires that the LCD and the SD card share a single SPI
|
91
|
90
|
|
92
|
91
|
#define ST7565_WRITE_BYTE(a) { spiSend((uint8_t)a); U8G_DELAY; }
|
|
@@ -129,8 +128,7 @@
|
129
|
128
|
|
130
|
129
|
uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
|
131
|
130
|
switch (msg) {
|
132
|
|
- case U8G_DEV_MSG_INIT:
|
133
|
|
- {
|
|
131
|
+ case U8G_DEV_MSG_INIT: {
|
134
|
132
|
OUT_WRITE(ST7565_CS_PIN, LOW);
|
135
|
133
|
#if ENABLED(SHARED_SPI)
|
136
|
134
|
u8g_Delay(250);
|
|
@@ -149,52 +147,50 @@ uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg
|
149
|
147
|
ST7565_NA0(); /* instruction mode */
|
150
|
148
|
ST7565_NCS(); /* enable chip */
|
151
|
149
|
|
152
|
|
-
|
153
|
|
- ST7565_WRITE_BYTE(0x0A2); /* 0x0a2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */
|
|
150
|
+ ST7565_WRITE_BYTE(0x0A2); /* 0x0A2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */
|
154
|
151
|
ST7565_WRITE_BYTE(0x0A0); /* Normal ADC Select (according to Displaytech 64128N datasheet) */
|
155
|
152
|
|
156
|
|
- ST7565_WRITE_BYTE(0x0c8); /* common output mode: set scan direction normal operation/SHL Select; 0x0c0 --> SHL = 0; normal; 0x0c8 --> SHL = 1 */
|
|
153
|
+ ST7565_WRITE_BYTE(0x0C8); /* common output mode: set scan direction normal operation/SHL Select; 0x0C0 --> SHL = 0; normal; 0x0C8 --> SHL = 1 */
|
157
|
154
|
ST7565_WRITE_BYTE(0x040); /* Display start line for Displaytech 64128N */
|
158
|
155
|
|
159
|
156
|
ST7565_WRITE_BYTE(0x028 | 0x04); /* power control: turn on voltage converter */
|
160
|
|
-// U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
|
|
157
|
+ //U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
|
161
|
158
|
|
162
|
159
|
ST7565_WRITE_BYTE(0x028 | 0x06); /* power control: turn on voltage regulator */
|
163
|
|
-// U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
|
|
160
|
+ //U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
|
164
|
161
|
|
165
|
162
|
ST7565_WRITE_BYTE(0x028 | 0x07); /* power control: turn on voltage follower */
|
166
|
|
-// U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
|
167
|
|
-
|
|
163
|
+ //U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
|
168
|
164
|
|
169
|
165
|
ST7565_WRITE_BYTE(0x010); /* Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N */
|
170
|
166
|
|
171
|
|
- ST7565_WRITE_BYTE(0x0a6); /* display normal, bit val 0: LCD pixel off. */
|
|
167
|
+ ST7565_WRITE_BYTE(0x0A6); /* display normal, bit val 0: LCD pixel off. */
|
172
|
168
|
|
173
|
169
|
ST7565_WRITE_BYTE(0x081); /* set contrast */
|
174
|
|
- ST7565_WRITE_BYTE(0x01e); /* Contrast value. Setting for controlling brightness of Displaytech 64128N */
|
|
170
|
+ ST7565_WRITE_BYTE(0x01E); /* Contrast value. Setting for controlling brightness of Displaytech 64128N */
|
175
|
171
|
|
176
|
|
-
|
177
|
|
- ST7565_WRITE_BYTE(0x0af); /* display on */
|
|
172
|
+ ST7565_WRITE_BYTE(0x0AF); /* display on */
|
178
|
173
|
|
179
|
174
|
U8G_ESC_DLY(100); /* delay 100 ms */
|
180
|
|
- ST7565_WRITE_BYTE(0x0a5); /* display all points; ST7565 */
|
|
175
|
+ ST7565_WRITE_BYTE(0x0A5); /* display all points; ST7565 */
|
181
|
176
|
U8G_ESC_DLY(100); /* delay 100 ms */
|
182
|
177
|
U8G_ESC_DLY(100); /* delay 100 ms */
|
183
|
|
- ST7565_WRITE_BYTE(0x0a4); /* normal display */
|
|
178
|
+ ST7565_WRITE_BYTE(0x0A4); /* normal display */
|
184
|
179
|
ST7565_CS(); /* disable chip */
|
185
|
180
|
} /* end of sequence */
|
186
|
|
- break;
|
187
|
|
- case U8G_DEV_MSG_STOP:
|
188
|
|
- break;
|
189
|
|
- case U8G_DEV_MSG_PAGE_NEXT:
|
190
|
|
- { u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
|
|
181
|
+ break;
|
|
182
|
+
|
|
183
|
+ case U8G_DEV_MSG_STOP: break;
|
|
184
|
+
|
|
185
|
+ case U8G_DEV_MSG_PAGE_NEXT: {
|
|
186
|
+ u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
|
191
|
187
|
ST7565_CS(); /* disable chip */
|
192
|
188
|
ST7565_NA0(); /* instruction mode */
|
193
|
189
|
ST7565_NCS(); /* enable chip */
|
194
|
190
|
ST7565_WRITE_BYTE(0x010); /* set upper 4 bit of the col adr to 0x10 */
|
195
|
191
|
ST7565_WRITE_BYTE(0x000); /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */
|
196
|
192
|
/* end of sequence */
|
197
|
|
- ST7565_WRITE_BYTE(0x0b0 | (2*pb->p.page));; /* select current page (ST7565R) */
|
|
193
|
+ ST7565_WRITE_BYTE(0x0B0 | (2*pb->p.page));; /* select current page (ST7565R) */
|
198
|
194
|
ST7565_A0(); /* data mode */
|
199
|
195
|
ST7560_WriteSequence( (uint8_t) pb->width, (uint8_t *)pb->buf);
|
200
|
196
|
ST7565_CS(); /* disable chip */
|
|
@@ -203,12 +199,13 @@ uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg
|
203
|
199
|
ST7565_WRITE_BYTE(0x010); /* set upper 4 bit of the col adr to 0x10 */
|
204
|
200
|
ST7565_WRITE_BYTE(0x000); /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */
|
205
|
201
|
/* end of sequence */
|
206
|
|
- ST7565_WRITE_BYTE(0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
|
|
202
|
+ ST7565_WRITE_BYTE(0x0B0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
|
207
|
203
|
ST7565_A0(); /* data mode */
|
208
|
204
|
ST7560_WriteSequence( (uint8_t) pb->width, (uint8_t *)(pb->buf)+pb->width);
|
209
|
205
|
ST7565_CS(); /* disable chip */
|
210
|
206
|
}
|
211
|
|
- break;
|
|
207
|
+ break;
|
|
208
|
+
|
212
|
209
|
case U8G_DEV_MSG_CONTRAST:
|
213
|
210
|
ST7565_NCS();
|
214
|
211
|
ST7565_NA0(); /* instruction mode */
|
|
@@ -216,21 +213,23 @@ uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg
|
216
|
213
|
ST7565_WRITE_BYTE((*(uint8_t *)arg) >> 2);
|
217
|
214
|
ST7565_CS(); /* disable chip */
|
218
|
215
|
return 1;
|
|
216
|
+
|
219
|
217
|
case U8G_DEV_MSG_SLEEP_ON:
|
220
|
218
|
ST7565_NA0(); /* instruction mode */
|
221
|
219
|
ST7565_NCS(); /* enable chip */
|
222
|
|
- ST7565_WRITE_BYTE(0x0ac); /* static indicator off */
|
|
220
|
+ ST7565_WRITE_BYTE(0x0AC); /* static indicator off */
|
223
|
221
|
ST7565_WRITE_BYTE(0x000); /* indicator register set (not sure if this is required) */
|
224
|
|
- ST7565_WRITE_BYTE(0x0ae); /* display off */
|
225
|
|
- ST7565_WRITE_BYTE(0x0a5); /* all points on */
|
|
222
|
+ ST7565_WRITE_BYTE(0x0AE); /* display off */
|
|
223
|
+ ST7565_WRITE_BYTE(0x0A5); /* all points on */
|
226
|
224
|
ST7565_CS(); /* disable chip , bugfix 12 nov 2014 */
|
227
|
225
|
/* end of sequence */
|
228
|
226
|
return 1;
|
|
227
|
+
|
229
|
228
|
case U8G_DEV_MSG_SLEEP_OFF:
|
230
|
229
|
ST7565_NA0(); /* instruction mode */
|
231
|
230
|
ST7565_NCS(); /* enable chip */
|
232
|
|
- ST7565_WRITE_BYTE(0x0a4); /* all points off */
|
233
|
|
- ST7565_WRITE_BYTE(0x0af); /* display on */
|
|
231
|
+ ST7565_WRITE_BYTE(0x0A4); /* all points off */
|
|
232
|
+ ST7565_WRITE_BYTE(0x0AF); /* display on */
|
234
|
233
|
U8G_ESC_DLY(50); /* delay 50 ms */
|
235
|
234
|
ST7565_CS(); /* disable chip , bugfix 12 nov 2014 */
|
236
|
235
|
/* end of sequence */
|
|
@@ -254,8 +253,6 @@ class U8GLIB_ST7565_64128n_2x_VIKI : public U8GLIB {
|
254
|
253
|
{ }
|
255
|
254
|
};
|
256
|
255
|
|
257
|
|
-
|
258
|
|
-
|
259
|
256
|
#pragma GCC reset_options
|
260
|
257
|
|
261
|
258
|
#endif // U8GLIB_ST7565
|