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-#ifdef TARGET_LPC1768
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-
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-#include "../spi_api.h"
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-
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-#include <lpc17xx_ssp.h>
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-#include <lpc17xx_pinsel.h>
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-#include <lpc17xx_gpio.h>
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-#include "lpc17xx_clkpwr.h"
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-
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-extern "C" void SSP0_IRQHandler(void);
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-extern "C" void SSP1_IRQHandler(void);
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-
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-namespace HAL {
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-namespace SPI {
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-
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-enum class SignalPolarity : uint8_t {
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- ACTIVE_LOW = 0,
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- ACTIVE_HIGH
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-};
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-
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-/* Hardware channels :
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- * 0: clk(0_7), mosi(0_9), miso(0_8), SSP1
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- * 1: clk(0_15), mosi(0_28), miso(0_17), SSP0
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-
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- * Logical channels:
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- * 0: hwchannel: 1, ssel(0_6)
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- * 1: hwchannel: 0, ssel(0_16)
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- * 2: hwchannel: 0, ssel(1_23)
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- */
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-
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-/*
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- * Defines the Hardware setup for an SPI channel
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- * The pins and (if applicable) the Hardware Peripheral
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- *
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- */
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-struct LogicalChannel; // who doesn't like circular dependencies
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-
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-struct HardwareChannel {
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- LPC_SSP_TypeDef *peripheral;
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- IRQn_Type IRQn;
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- uint8_t clk_port;
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- uint8_t clk_pin;
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- uint8_t mosi_port;
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- uint8_t mosi_pin;
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- uint8_t miso_port;
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- uint8_t miso_pin;
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- SSP_DATA_SETUP_Type xfer_config;
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- volatile FlagStatus xfer_complete;
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- bool initialised;
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- volatile bool in_use;
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- LogicalChannel* active_channel;
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-} hardware_channels[2] = {
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- {LPC_SSP0, SSP0_IRQn, 0, 15, 0, 18, 0, 17, { nullptr, 0, nullptr, 0, 0, SSP_STAT_DONE }, RESET, false, false, nullptr},
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- {LPC_SSP1, SSP1_IRQn, 0, 7, 0, 9, 0, 8 , { nullptr, 0, nullptr, 0, 0, SSP_STAT_DONE }, RESET, false, false, nullptr}
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-};
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-
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-/*
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- * Define all available logical SPI ports
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- */
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-struct LogicalChannel {
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- HardwareChannel& hw_channel;
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- uint8_t ssel_port;
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- uint8_t ssel_pin;
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- SignalPolarity ssel_polarity;
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- bool ssel_override;
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- SSP_CFG_Type config;
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- uint32_t CR0;
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- uint32_t CPSR;
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-} logical_channels[3] = {
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- { hardware_channels[1], 0, 6, SignalPolarity::ACTIVE_LOW, false, { SSP_DATABIT_8, SSP_CPHA_FIRST, SSP_CPOL_HI, SSP_MASTER_MODE, SSP_FRAME_SPI, 1000000 }, 0, 0 },
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- { hardware_channels[0], 0, 16, SignalPolarity::ACTIVE_HIGH, true, { SSP_DATABIT_8, SSP_CPHA_FIRST, SSP_CPOL_HI, SSP_MASTER_MODE, SSP_FRAME_SPI, 1000000 }, 0, 0 },
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- { hardware_channels[0], 1, 23, SignalPolarity::ACTIVE_LOW, true, { SSP_DATABIT_8, SSP_CPHA_FIRST, SSP_CPOL_HI, SSP_MASTER_MODE, SSP_FRAME_SPI, 1000000 }, 0, 0 }
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-};
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-
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-//Internal functions
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-extern "C" void ssp_irq_handler(uint8_t hw_channel);
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-LogicalChannel* get_logical_channel(uint8_t channel);
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-bool set_ssel(LogicalChannel* logical_channel);
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-void clear_ssel(LogicalChannel* logical_channel);
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-void restore_frequency(LogicalChannel* logical_channel);
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-
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-LogicalChannel* get_logical_channel(uint8_t channel) {
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- if(channel > sizeof(logical_channels) - 1) {
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- return nullptr;
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- }
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- return &logical_channels[channel];
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-}
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-
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-bool set_ssel(LogicalChannel* logical_channel) {
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- if(logical_channel->hw_channel.in_use == true) {
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- return false;
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- }
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-
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- if(logical_channel->ssel_polarity == SignalPolarity::ACTIVE_HIGH) {
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- GPIO_SetValue(logical_channel->ssel_port, (1 << logical_channel->ssel_pin));
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- } else {
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- GPIO_ClearValue(logical_channel->ssel_port, (1 << logical_channel->ssel_pin));
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- }
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- logical_channel->hw_channel.in_use = true;
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-
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- return true;
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-}
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-
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-void clear_ssel(LogicalChannel* logical_channel) {
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- if(logical_channel->ssel_polarity == SignalPolarity::ACTIVE_HIGH) {
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- GPIO_ClearValue(logical_channel->ssel_port, (1 << logical_channel->ssel_pin));
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- } else {
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- GPIO_SetValue(logical_channel->ssel_port, (1 << logical_channel->ssel_pin));
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- }
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- logical_channel->hw_channel.in_use = false;
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-}
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-
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-void restore_frequency(LogicalChannel* logical_channel) {
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- logical_channel->hw_channel.peripheral->CR0 = logical_channel->CR0;
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- logical_channel->hw_channel.peripheral->CPSR = logical_channel->CPSR;
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-}
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-
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-/*
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- * SPI API Implementation
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- */
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-bool initialise(uint8_t channel) {
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- LogicalChannel* logical_channel = get_logical_channel(channel);
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- if(logical_channel == nullptr) return false;
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- HardwareChannel& hw_channel = logical_channel->hw_channel;
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-
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- PINSEL_CFG_Type pin_cfg;
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- pin_cfg.OpenDrain = PINSEL_PINMODE_NORMAL;
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- pin_cfg.Pinmode = PINSEL_PINMODE_PULLUP;
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-
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- if(hw_channel.initialised == false) {
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- pin_cfg.Funcnum = 2; //ssp (spi) function
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- pin_cfg.Portnum = hw_channel.clk_port;
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- pin_cfg.Pinnum = hw_channel.clk_pin;
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- PINSEL_ConfigPin(&pin_cfg); //clk
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-
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- pin_cfg.Portnum = hw_channel.miso_port;
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- pin_cfg.Pinnum = hw_channel.miso_pin;
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- PINSEL_ConfigPin(&pin_cfg); //miso
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-
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- pin_cfg.Portnum = hw_channel.mosi_port;
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- pin_cfg.Pinnum = hw_channel.mosi_pin;
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- PINSEL_ConfigPin(&pin_cfg); //mosi
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-
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- SSP_Init(hw_channel.peripheral, &logical_channel->config);
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- logical_channel->CR0 = logical_channel->hw_channel.peripheral->CR0; // preserve for restore
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- logical_channel->CPSR = logical_channel->hw_channel.peripheral->CPSR; // preserve for restore
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- SSP_Cmd(hw_channel.peripheral, ENABLE);
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-
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- hw_channel.initialised = true;
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- hw_channel.active_channel = logical_channel;
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-
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- //NVIC_SetPriority(hw_channel.IRQn, NVIC_EncodePriority(0, 3, 0)); //Very Low priority
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- //NVIC_EnableIRQ(hw_channel.IRQn);
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- }
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-
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- pin_cfg.Portnum = logical_channel->ssel_port;
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- pin_cfg.Pinnum = logical_channel->ssel_pin;
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- pin_cfg.Pinmode = logical_channel->ssel_polarity == SignalPolarity::ACTIVE_LOW ? PINSEL_PINMODE_PULLUP : PINSEL_PINMODE_PULLDOWN;
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- pin_cfg.Funcnum = 0; //gpio function
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- PINSEL_ConfigPin(&pin_cfg); //ssel
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-
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- GPIO_SetDir(logical_channel->ssel_port, (1 << logical_channel->ssel_pin), 1);
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- GPIO_SetValue(logical_channel->ssel_port, (1 << logical_channel->ssel_pin));
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- return true;
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-}
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-
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-bool enable_cs(uint8_t channel) {
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- LogicalChannel* logical_channel = get_logical_channel(channel);
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- if(logical_channel == nullptr) return false;
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- return set_ssel(logical_channel);
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-}
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-
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-void disable_cs(uint8_t channel) {
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- LogicalChannel* logical_channel = get_logical_channel(channel);
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- if(logical_channel == nullptr) return;
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- if(logical_channel->hw_channel.in_use && !logical_channel->ssel_override) return; //automatic SSel wasn't overridden
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-
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- clear_ssel(logical_channel);
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-}
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-
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-void set_frequency(uint8_t channel, uint32_t frequency) {
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- LogicalChannel* logical_channel = get_logical_channel(channel);
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- if(logical_channel == nullptr) return;
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-
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- SSP_Cmd(logical_channel->hw_channel.peripheral, DISABLE);
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- uint32_t prescale, cr0_div, cmp_clk, ssp_clk;
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-
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- if (logical_channel->hw_channel.peripheral == LPC_SSP0){
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- ssp_clk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_SSP0);
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- } else if (logical_channel->hw_channel.peripheral == LPC_SSP1) {
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- ssp_clk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_SSP1);
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- } else {
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- return;
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- }
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- //find the closest clock divider / prescaler
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- cr0_div = 0;
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- cmp_clk = 0xFFFFFFFF;
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- prescale = 2;
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- while (cmp_clk > frequency) {
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- cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
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- if (cmp_clk > frequency) {
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- cr0_div++;
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- if (cr0_div > 0xFF) {
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- cr0_div = 0;
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- prescale += 2;
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- }
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- }
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- }
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-
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- logical_channel->hw_channel.peripheral->CR0 &= (~SSP_CR0_SCR(0xFF)) & SSP_CR0_BITMASK;
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- logical_channel->hw_channel.peripheral->CR0 |= (SSP_CR0_SCR(cr0_div)) & SSP_CR0_BITMASK;
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- logical_channel->CR0 = logical_channel->hw_channel.peripheral->CR0; // preserve for restore
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-
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- logical_channel->hw_channel.peripheral->CPSR = prescale & SSP_CPSR_BITMASK;
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- logical_channel->CPSR = logical_channel->hw_channel.peripheral->CPSR; // preserve for restore
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-
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- logical_channel->config.ClockRate = ssp_clk / ((cr0_div + 1) * prescale);
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-
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- SSP_Cmd(logical_channel->hw_channel.peripheral, ENABLE);
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-}
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-
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-void read(uint8_t channel, uint8_t *buffer, uint32_t length) {
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- transfer(channel, nullptr, buffer, length);
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-}
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-
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-uint8_t read(uint8_t channel) {
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- uint8_t buffer;
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- transfer(channel, nullptr, &buffer, 1);
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- return buffer;
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-}
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-
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-void write(uint8_t channel, const uint8_t *buffer, uint32_t length) {
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- transfer(channel, buffer, nullptr, length);
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-}
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-
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-void write(uint8_t channel, uint8_t value) {
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- transfer(channel, &value, nullptr, 1);
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-}
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-
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-void transfer(uint8_t channel, const uint8_t *buffer_write, uint8_t *buffer_read, uint32_t length) {
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- LogicalChannel* logical_channel = get_logical_channel(channel);
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- if(logical_channel == nullptr) return;
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-
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- if((logical_channel->hw_channel.in_use && !logical_channel->ssel_override) || !logical_channel->hw_channel.initialised) return;
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- if(!logical_channel->ssel_override) {
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- if(!set_ssel(logical_channel)) return;
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- }
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-
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- if(logical_channel != logical_channel->hw_channel.active_channel) {
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- restore_frequency(logical_channel);
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- logical_channel->hw_channel.active_channel = logical_channel;
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- }
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-
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- logical_channel->hw_channel.xfer_config.tx_data = (void *)buffer_write;
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- logical_channel->hw_channel.xfer_config.rx_data = (void *)buffer_read;
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- logical_channel->hw_channel.xfer_config.length = length;
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-
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- (void)SSP_ReadWrite(logical_channel->hw_channel.peripheral, &logical_channel->hw_channel.xfer_config, SSP_TRANSFER_POLLING); //SSP_TRANSFER_INTERRUPT
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-
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- if(!logical_channel->ssel_override) {
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- clear_ssel(logical_channel->hw_channel.active_channel);
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- }
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-}
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-
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-uint8_t transfer(uint8_t channel, uint8_t value) {
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- uint8_t buffer;
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- transfer(channel, &value, &buffer, 1);
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- return buffer;
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-}
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-
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-/*
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- * Interrupt Handlers
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- */
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-extern "C" void ssp_irq_handler(uint8_t hw_channel) {
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-
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- SSP_DATA_SETUP_Type *xf_setup;
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- uint32_t tmp;
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- uint8_t dataword;
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-
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- // Disable all SSP interrupts
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- SSP_IntConfig(hardware_channels[hw_channel].peripheral, SSP_INTCFG_ROR | SSP_INTCFG_RT | SSP_INTCFG_RX | SSP_INTCFG_TX, DISABLE);
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-
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- dataword = (SSP_GetDataSize(hardware_channels[hw_channel].peripheral) > 8) ? 1 : 0;
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-
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- xf_setup = &hardware_channels[hw_channel].xfer_config;
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- // save status
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- tmp = SSP_GetRawIntStatusReg(hardware_channels[hw_channel].peripheral);
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- xf_setup->status = tmp;
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-
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- // Check overrun error
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- if (tmp & SSP_RIS_ROR) {
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- // Clear interrupt
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- SSP_ClearIntPending(hardware_channels[hw_channel].peripheral, SSP_INTCLR_ROR);
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- // update status
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- xf_setup->status |= SSP_STAT_ERROR;
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- // Set Complete Flag
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- hardware_channels[hw_channel].xfer_complete = SET;
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- if(!hardware_channels[hw_channel].active_channel->ssel_override) clear_ssel(hardware_channels[hw_channel].active_channel);
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- return;
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- }
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-
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- if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
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- /* check if RX FIFO contains data */
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- while ((SSP_GetStatus(hardware_channels[hw_channel].peripheral, SSP_STAT_RXFIFO_NOTEMPTY)) && (xf_setup->rx_cnt != xf_setup->length)) {
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- // Read data from SSP data
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- tmp = SSP_ReceiveData(hardware_channels[hw_channel].peripheral);
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-
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- // Store data to destination
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- if (xf_setup->rx_data != nullptr) {
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- if (dataword == 0) {
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- *(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = (uint8_t) tmp;
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312
|
|
- } else {
|
313
|
|
- *(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = (uint16_t) tmp;
|
314
|
|
- }
|
315
|
|
- }
|
316
|
|
- // Increase counter
|
317
|
|
- if (dataword == 0) {
|
318
|
|
- xf_setup->rx_cnt++;
|
319
|
|
- } else {
|
320
|
|
- xf_setup->rx_cnt += 2;
|
321
|
|
- }
|
322
|
|
- }
|
323
|
|
-
|
324
|
|
- while ((SSP_GetStatus(hardware_channels[hw_channel].peripheral, SSP_STAT_TXFIFO_NOTFULL)) && (xf_setup->tx_cnt != xf_setup->length)) {
|
325
|
|
- // Write data to buffer
|
326
|
|
- if (xf_setup->tx_data == nullptr) {
|
327
|
|
- if (dataword == 0) {
|
328
|
|
- SSP_SendData(hardware_channels[hw_channel].peripheral, 0xFF);
|
329
|
|
- xf_setup->tx_cnt++;
|
330
|
|
- } else {
|
331
|
|
- SSP_SendData(hardware_channels[hw_channel].peripheral, 0xFFFF);
|
332
|
|
- xf_setup->tx_cnt += 2;
|
333
|
|
- }
|
334
|
|
- } else {
|
335
|
|
- if (dataword == 0) {
|
336
|
|
- SSP_SendData(hardware_channels[hw_channel].peripheral, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
|
337
|
|
- xf_setup->tx_cnt++;
|
338
|
|
- } else {
|
339
|
|
- SSP_SendData(hardware_channels[hw_channel].peripheral, (*(uint16_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
|
340
|
|
- xf_setup->tx_cnt += 2;
|
341
|
|
- }
|
342
|
|
- }
|
343
|
|
-
|
344
|
|
- // Check overrun error
|
345
|
|
- if (SSP_GetRawIntStatus(hardware_channels[hw_channel].peripheral, SSP_INTSTAT_RAW_ROR)) {
|
346
|
|
- // update status
|
347
|
|
- xf_setup->status |= SSP_STAT_ERROR;
|
348
|
|
- // Set Complete Flag
|
349
|
|
- hardware_channels[hw_channel].xfer_complete = SET;
|
350
|
|
- if(!hardware_channels[hw_channel].active_channel->ssel_override) clear_ssel(hardware_channels[hw_channel].active_channel);
|
351
|
|
- return;
|
352
|
|
- }
|
353
|
|
-
|
354
|
|
- // Check for any data available in RX FIFO
|
355
|
|
- while ((SSP_GetStatus(hardware_channels[hw_channel].peripheral, SSP_STAT_RXFIFO_NOTEMPTY)) && (xf_setup->rx_cnt != xf_setup->length)) {
|
356
|
|
- // Read data from SSP data
|
357
|
|
- tmp = SSP_ReceiveData(hardware_channels[hw_channel].peripheral);
|
358
|
|
-
|
359
|
|
- // Store data to destination
|
360
|
|
- if (xf_setup->rx_data != nullptr) {
|
361
|
|
- if (dataword == 0) {
|
362
|
|
- *(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = (uint8_t) tmp;
|
363
|
|
- } else {
|
364
|
|
- *(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = (uint16_t) tmp;
|
365
|
|
- }
|
366
|
|
- }
|
367
|
|
- // Increase counter
|
368
|
|
- if (dataword == 0) {
|
369
|
|
- xf_setup->rx_cnt++;
|
370
|
|
- } else {
|
371
|
|
- xf_setup->rx_cnt += 2;
|
372
|
|
- }
|
373
|
|
- }
|
374
|
|
- }
|
375
|
|
- }
|
376
|
|
-
|
377
|
|
- // If there more data to sent or receive
|
378
|
|
- if ((xf_setup->rx_cnt != xf_setup->length) || (xf_setup->tx_cnt != xf_setup->length)) {
|
379
|
|
- // Enable all interrupt
|
380
|
|
- SSP_IntConfig(hardware_channels[hw_channel].peripheral, SSP_INTCFG_ROR | SSP_INTCFG_RT | SSP_INTCFG_RX | SSP_INTCFG_TX, ENABLE);
|
381
|
|
- } else {
|
382
|
|
- // Save status
|
383
|
|
- xf_setup->status = SSP_STAT_DONE;
|
384
|
|
- // Set Complete Flag
|
385
|
|
- hardware_channels[hw_channel].xfer_complete = SET;
|
386
|
|
- if(!hardware_channels[hw_channel].active_channel->ssel_override) clear_ssel(hardware_channels[hw_channel].active_channel);
|
387
|
|
- }
|
388
|
|
-}
|
389
|
|
-
|
390
|
|
-}
|
391
|
|
-}
|
392
|
|
-
|
393
|
|
-extern "C" void SSP0_IRQHandler(void) {
|
394
|
|
- HAL::SPI::ssp_irq_handler(0);
|
395
|
|
-}
|
396
|
|
-
|
397
|
|
-extern "C" void SSP1_IRQHandler(void) {
|
398
|
|
- HAL::SPI::ssp_irq_handler(1);
|
399
|
|
-}
|
400
|
|
-
|
401
|
|
-
|
402
|
|
-#endif
|