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@@ -102,7 +102,7 @@ void HardwareSerial::begin(uint32_t baudrate) {
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// Initialize eripheral with given to corresponding parameter
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UART_Init(UARTx, &UARTConfigStruct);
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// Enable and reset the TX and RX FIFOs
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UART_FIFOConfigStructInit(&FIFOConfig);
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UART_FIFOConfig(UARTx, &FIFOConfig);
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@@ -113,7 +113,7 @@ void HardwareSerial::begin(uint32_t baudrate) {
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// Configure Interrupts
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UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
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UART_IntConfig(UARTx, UART_INTCFG_RLS, ENABLE);
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+
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if (UARTx == LPC_UART0)
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NVIC_EnableIRQ(UART0_IRQn);
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else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
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@@ -135,13 +135,13 @@ int HardwareSerial::peek() {
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/* Temporarily lock out UART receive interrupts during this read so the UART receive
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interrupt won't cause problems with the index values */
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UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
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if (RxQueueReadPos != RxQueueWritePos)
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byte = RxBuffer[RxQueueReadPos];
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/* Re-enable UART interrupts */
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UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
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+
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return byte;
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}
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@@ -151,7 +151,7 @@ int HardwareSerial::read() {
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/* Temporarily lock out UART receive interrupts during this read so the UART receive
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interrupt won't cause problems with the index values */
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UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
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if (RxQueueReadPos != RxQueueWritePos) {
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byte = RxBuffer[RxQueueReadPos];
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RxQueueReadPos = (RxQueueReadPos + 1) % RX_BUFFER_SIZE;
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@@ -159,7 +159,7 @@ int HardwareSerial::read() {
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/* Re-enable UART interrupts */
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UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
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return byte;
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}
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@@ -170,7 +170,7 @@ size_t HardwareSerial::write(uint8_t send) {
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/* If the Tx Buffer is full, wait for space to clear */
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if ((TxQueueWritePos+1) % TX_BUFFER_SIZE == TxQueueReadPos) flushTX();
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/* Temporarily lock out UART transmit interrupts during this read so the UART transmit interrupt won't
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cause problems with the index values */
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UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
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@@ -180,7 +180,7 @@ size_t HardwareSerial::write(uint8_t send) {
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fifolvl = *(reinterpret_cast<volatile uint32_t *>(&((LPC_UART1_TypeDef *) UARTx)->FIFOLVL));
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else
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fifolvl = *(reinterpret_cast<volatile uint32_t *>(&UARTx->FIFOLVL));
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/* If the queue is empty and there's space in the FIFO, immediately send the byte */
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if (TxQueueWritePos == TxQueueReadPos && fifolvl < UART_TX_FIFO_SIZE) {
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bytes = UART_Send(UARTx, &send, 1, BLOCKING);
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@@ -191,10 +191,10 @@ size_t HardwareSerial::write(uint8_t send) {
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TxQueueWritePos = (TxQueueWritePos+1) % TX_BUFFER_SIZE;
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bytes++;
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}
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/* Re-enable the TX Interrupt */
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UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
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return bytes;
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#else
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return UART_Send(UARTx, &send, 1, BLOCKING);
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@@ -251,7 +251,7 @@ void HardwareSerial::IRQHandler() {
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return;
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}
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}
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+
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if ( IIRValue == UART_IIR_INTID_RDA ) /* Receive Data Available */
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{
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/* Clear the FIFO */
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@@ -278,7 +278,7 @@ void HardwareSerial::IRQHandler() {
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/* Wait for FIFO buffer empty */
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while (UART_CheckBusy(UARTx) == SET);
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/* Transfer up to UART_TX_FIFO_SIZE bytes of data */
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for (int i = 0; i < UART_TX_FIFO_SIZE && TxQueueWritePos != TxQueueReadPos; i++) {
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/* Move a piece of data into the transmit FIFO */
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@@ -287,7 +287,7 @@ void HardwareSerial::IRQHandler() {
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else
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break;
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}
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+
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/* If there is no more data to send, disable the transmit interrupt - else enable it or keep it enabled */
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if (TxQueueWritePos == TxQueueReadPos)
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UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
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