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Cleanup for HAL_spi_Due.cpp

Scott Lahteine 6 vuotta sitten
vanhempi
commit
bc75eb2c64
1 muutettua tiedostoa jossa 120 lisäystä ja 125 poistoa
  1. 120
    125
      Marlin/src/HAL/HAL_DUE/HAL_spi_Due.cpp

+ 120
- 125
Marlin/src/HAL/HAL_DUE/HAL_spi_Due.cpp Näytä tiedosto

@@ -581,84 +581,124 @@
581 581
     // --------------------------------------------------------------------------
582 582
     // hardware SPI
583 583
     // --------------------------------------------------------------------------
584
-    // 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
585
-    int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
586
-    bool spiInitMaded = false;
584
+    static bool spiInitialized = false;
585
+
586
+    void spiInit(uint8_t spiRate) {
587
+      if (spiInitialized) return;
588
+
589
+      // 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
590
+      constexpr int spiDivider[] = { 10, 21, 42, 84, 168, 255, 255 };
591
+      if (spiRate > 6) spiRate = 1;
592
+
593
+      // Set SPI mode 1, clock, select not active after transfer, with delay between transfers
594
+      SPI_ConfigureNPCS(SPI0, SPI_CHAN_DAC,
595
+                        SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDivider[spiRate]) |
596
+                        SPI_CSR_DLYBCT(1));
597
+      // Set SPI mode 0, clock, select not active after transfer, with delay between transfers
598
+      SPI_ConfigureNPCS(SPI0, SPI_CHAN_EEPROM1, SPI_CSR_NCPHA |
599
+                        SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDivider[spiRate]) |
600
+                        SPI_CSR_DLYBCT(1));
601
+
602
+      // Set SPI mode 0, clock, select not active after transfer, with delay between transfers
603
+      SPI_ConfigureNPCS(SPI0, SPI_CHAN, SPI_CSR_NCPHA |
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+                        SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDivider[spiRate]) |
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+                        SPI_CSR_DLYBCT(1));
606
+      SPI_Enable(SPI0);
607
+      spiInitialized = true;
608
+    }
587 609
 
588 610
     void spiBegin() {
589
-      if (spiInitMaded == false) {
590
-        // Configure SPI pins
591
-        PIO_Configure(
592
-           g_APinDescription[SCK_PIN].pPort,
593
-           g_APinDescription[SCK_PIN].ulPinType,
594
-           g_APinDescription[SCK_PIN].ulPin,
595
-           g_APinDescription[SCK_PIN].ulPinConfiguration);
596
-        PIO_Configure(
597
-           g_APinDescription[MOSI_PIN].pPort,
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-           g_APinDescription[MOSI_PIN].ulPinType,
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-           g_APinDescription[MOSI_PIN].ulPin,
600
-           g_APinDescription[MOSI_PIN].ulPinConfiguration);
601
-        PIO_Configure(
602
-           g_APinDescription[MISO_PIN].pPort,
603
-           g_APinDescription[MISO_PIN].ulPinType,
604
-           g_APinDescription[MISO_PIN].ulPin,
605
-           g_APinDescription[MISO_PIN].ulPinConfiguration);
606
-
607
-        // set master mode, peripheral select, fault detection
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-        SPI_Configure(SPI0, ID_SPI0, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PS);
609
-        SPI_Enable(SPI0);
610
-
611
-        #if MB(ALLIGATOR)
612
-          SET_OUTPUT(DAC0_SYNC);
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-          #if EXTRUDERS > 1
614
-            SET_OUTPUT(DAC1_SYNC);
615
-            WRITE(DAC1_SYNC, HIGH);
616
-          #endif
617
-          SET_OUTPUT(SPI_EEPROM1_CS);
618
-          SET_OUTPUT(SPI_EEPROM2_CS);
619
-          SET_OUTPUT(SPI_FLASH_CS);
620
-          WRITE(DAC0_SYNC, HIGH);
621
-          WRITE(SPI_EEPROM1_CS, HIGH );
622
-          WRITE(SPI_EEPROM2_CS, HIGH );
623
-          WRITE(SPI_FLASH_CS, HIGH );
624
-          WRITE(SS_PIN, HIGH );
625
-        #endif // MB(ALLIGATOR)
626
-
627
-        OUT_WRITE(SDSS,0);
628
-
629
-        PIO_Configure(
630
-          g_APinDescription[SPI_PIN].pPort,
631
-          g_APinDescription[SPI_PIN].ulPinType,
632
-          g_APinDescription[SPI_PIN].ulPin,
633
-          g_APinDescription[SPI_PIN].ulPinConfiguration);
634
-
635
-        spiInit(1);
636
-        spiInitMaded = true;
637
-      }
611
+      if (spiInitialized) return;
612
+
613
+      // Configure SPI pins
614
+      PIO_Configure(
615
+         g_APinDescription[SCK_PIN].pPort,
616
+         g_APinDescription[SCK_PIN].ulPinType,
617
+         g_APinDescription[SCK_PIN].ulPin,
618
+         g_APinDescription[SCK_PIN].ulPinConfiguration);
619
+      PIO_Configure(
620
+         g_APinDescription[MOSI_PIN].pPort,
621
+         g_APinDescription[MOSI_PIN].ulPinType,
622
+         g_APinDescription[MOSI_PIN].ulPin,
623
+         g_APinDescription[MOSI_PIN].ulPinConfiguration);
624
+      PIO_Configure(
625
+         g_APinDescription[MISO_PIN].pPort,
626
+         g_APinDescription[MISO_PIN].ulPinType,
627
+         g_APinDescription[MISO_PIN].ulPin,
628
+         g_APinDescription[MISO_PIN].ulPinConfiguration);
629
+
630
+      // set master mode, peripheral select, fault detection
631
+      SPI_Configure(SPI0, ID_SPI0, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PS);
632
+      SPI_Enable(SPI0);
633
+
634
+      SET_OUTPUT(DAC0_SYNC);
635
+      #if EXTRUDERS > 1
636
+        SET_OUTPUT(DAC1_SYNC);
637
+        WRITE(DAC1_SYNC, HIGH);
638
+      #endif
639
+      SET_OUTPUT(SPI_EEPROM1_CS);
640
+      SET_OUTPUT(SPI_EEPROM2_CS);
641
+      SET_OUTPUT(SPI_FLASH_CS);
642
+      WRITE(DAC0_SYNC, HIGH);
643
+      WRITE(SPI_EEPROM1_CS, HIGH );
644
+      WRITE(SPI_EEPROM2_CS, HIGH );
645
+      WRITE(SPI_FLASH_CS, HIGH );
646
+      WRITE(SS_PIN, HIGH );
647
+
648
+      OUT_WRITE(SDSS,0);
649
+
650
+      PIO_Configure(
651
+        g_APinDescription[SPI_PIN].pPort,
652
+        g_APinDescription[SPI_PIN].ulPinType,
653
+        g_APinDescription[SPI_PIN].ulPin,
654
+        g_APinDescription[SPI_PIN].ulPinConfiguration);
655
+
656
+      spiInit(1);
638 657
     }
639 658
 
640
-    void spiInit(uint8_t spiRate) {
641
-      if (spiInitMaded == false) {
642
-        if (spiRate > 6) spiRate = 1;
643
-
644
-        #if MB(ALLIGATOR)
645
-          // Set SPI mode 1, clock, select not active after transfer, with delay between transfers
646
-          SPI_ConfigureNPCS(SPI0, SPI_CHAN_DAC,
647
-                            SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
648
-                            SPI_CSR_DLYBCT(1));
649
-          // Set SPI mode 0, clock, select not active after transfer, with delay between transfers
650
-          SPI_ConfigureNPCS(SPI0, SPI_CHAN_EEPROM1, SPI_CSR_NCPHA |
651
-                            SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
652
-                            SPI_CSR_DLYBCT(1));
653
-        #endif//MB(ALLIGATOR)
654
-
655
-        // Set SPI mode 0, clock, select not active after transfer, with delay between transfers
656
-        SPI_ConfigureNPCS(SPI0, SPI_CHAN, SPI_CSR_NCPHA |
657
-                          SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
658
-                          SPI_CSR_DLYBCT(1));
659
-        SPI_Enable(SPI0);
660
-        spiInitMaded = true;
659
+    // Read single byte from SPI
660
+    uint8_t spiRec() {
661
+      // write dummy byte with address and end transmission flag
662
+      SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
663
+      // wait for transmit register empty
664
+      while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
665
+
666
+      // wait for receive register
667
+      while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
668
+      // get byte from receive register
669
+      //DELAY_US(1U);
670
+      return SPI0->SPI_RDR;
671
+    }
672
+
673
+    uint8_t spiRec(uint32_t chan) {
674
+      uint8_t spirec_tmp;
675
+      // wait for transmit register empty
676
+      while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
677
+      while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
678
+        spirec_tmp =  SPI0->SPI_RDR;
679
+        UNUSED(spirec_tmp);
680
+
681
+      // write dummy byte with address and end transmission flag
682
+      SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER;
683
+
684
+      // wait for receive register
685
+      while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
686
+      // get byte from receive register
687
+      return SPI0->SPI_RDR;
688
+    }
689
+
690
+    // Read from SPI into buffer
691
+    void spiRead(uint8_t* buf, uint16_t nbyte) {
692
+      if (nbyte-- == 0) return;
693
+
694
+      for (int i = 0; i < nbyte; i++) {
695
+        //while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
696
+        SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN);
697
+        while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
698
+        buf[i] = SPI0->SPI_RDR;
699
+        //DELAY_US(1U);
661 700
       }
701
+      buf[nbyte] = spiRec();
662 702
     }
663 703
 
664 704
     // Write single byte to SPI
@@ -714,51 +754,6 @@
714 754
       spiSend(chan, buf[n - 1]);
715 755
     }
716 756
 
717
-    // Read single byte from SPI
718
-    uint8_t spiRec() {
719
-      // write dummy byte with address and end transmission flag
720
-      SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
721
-      // wait for transmit register empty
722
-      while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
723
-
724
-      // wait for receive register
725
-      while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
726
-      // get byte from receive register
727
-      //DELAY_US(1U);
728
-      return SPI0->SPI_RDR;
729
-    }
730
-
731
-    uint8_t spiRec(uint32_t chan) {
732
-      uint8_t spirec_tmp;
733
-      // wait for transmit register empty
734
-      while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
735
-      while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
736
-        spirec_tmp =  SPI0->SPI_RDR;
737
-        UNUSED(spirec_tmp);
738
-
739
-      // write dummy byte with address and end transmission flag
740
-      SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER;
741
-
742
-      // wait for receive register
743
-      while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
744
-      // get byte from receive register
745
-      return SPI0->SPI_RDR;
746
-    }
747
-
748
-    // Read from SPI into buffer
749
-    void spiRead(uint8_t* buf, uint16_t nbyte) {
750
-      if (nbyte-- == 0) return;
751
-
752
-      for (int i = 0; i < nbyte; i++) {
753
-        //while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
754
-        SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN);
755
-        while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
756
-        buf[i] = SPI0->SPI_RDR;
757
-        //DELAY_US(1U);
758
-      }
759
-      buf[nbyte] = spiRec();
760
-    }
761
-
762 757
     // Write from buffer to SPI
763 758
     void spiSendBlock(uint8_t token, const uint8_t* buf) {
764 759
       SPI0->SPI_TDR = (uint32_t)token | SPI_PCS(SPI_CHAN);
@@ -780,7 +775,7 @@
780 775
       // TODO: to be implemented
781 776
     }
782 777
 
783
-  #else  // U8G compatible hardware SPI
778
+  #else // U8G compatible hardware SPI
784 779
 
785 780
     #define SPI_MODE_0_DUE_HW 2  // DUE CPHA control bit is inverted
786 781
     #define SPI_MODE_1_DUE_HW 3
@@ -789,7 +784,7 @@
789 784
 
790 785
     void spiInit(uint8_t spiRate=6) {  // Default to slowest rate if not specified)
791 786
       // 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
792
-      int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
787
+      constexpr int spiDivider[] = { 10, 21, 42, 84, 168, 255, 255 };
793 788
       if (spiRate > 6) spiRate = 1;
794 789
 
795 790
       // Enable PIOA and SPI0
@@ -809,7 +804,11 @@
809 804
       // Master mode, no fault detection, PCS bits in data written to TDR select CSR register
810 805
       SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PS | SPI_MR_MODFDIS;
811 806
       // SPI mode 0, 8 Bit data transfer, baud rate
812
-      SPI0->SPI_CSR[3] = SPI_CSR_SCBR(spiDueDividors[spiRate]) | SPI_CSR_CSAAT | SPI_MODE_0_DUE_HW;  // use same CSR as TMC2130
807
+      SPI0->SPI_CSR[3] = SPI_CSR_SCBR(spiDivider[spiRate]) | SPI_CSR_CSAAT | SPI_MODE_0_DUE_HW;  // use same CSR as TMC2130
808
+    }
809
+
810
+    void spiBegin() {
811
+      spiInit();
813 812
     }
814 813
 
815 814
     static uint8_t spiTransfer(uint8_t data) {
@@ -828,10 +827,6 @@
828 827
       return SPI0->SPI_RDR;
829 828
     }
830 829
 
831
-    void spiBegin() {
832
-      spiInit();
833
-    }
834
-
835 830
     uint8_t spiRec() {
836 831
       uint8_t data = spiTransfer(0xFF);
837 832
       return data;

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