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@@ -20,124 +20,126 @@
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20
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20
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/* Validate address */
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21
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22
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#ifdef ARDUINO_ARCH_SAM
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23
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-// For DUE, valid address ranges are
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24
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-// SRAM (0x20070000 - 0x20088000) (96kb)
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25
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-// FLASH (0x00080000 - 0x00100000) (512kb)
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26
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-//
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27
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-#define START_SRAM_ADDR 0x20070000
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28
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-#define END_SRAM_ADDR 0x20088000
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-#define START_FLASH_ADDR 0x00080000
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-#define END_FLASH_ADDR 0x00100000
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-#endif
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32
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-
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33
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-#ifdef TARGET_LPC1768
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-// For LPC1769:
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35
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-// SRAM (0x10000000 - 0x10008000) (32kb)
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36
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-// FLASH (0x00000000 - 0x00080000) (512kb)
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-//
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-#define START_SRAM_ADDR 0x10000000
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-#define END_SRAM_ADDR 0x10008000
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40
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-#define START_FLASH_ADDR 0x00000000
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-#define END_FLASH_ADDR 0x00080000
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42
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-#endif
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-
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-#if 0
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-// For STM32F103CBT6
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46
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-// SRAM (0x20000000 - 0x20005000) (20kb)
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47
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-// FLASH (0x00000000 - 0x00020000) (128kb)
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48
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-//
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49
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-#define START_SRAM_ADDR 0x20000000
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50
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-#define END_SRAM_ADDR 0x20005000
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51
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-#define START_FLASH_ADDR 0x00000000
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-#define END_FLASH_ADDR 0x00020000
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-#endif
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23
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55
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-#if defined(__STM32F1__) || defined(STM32F1xx) || defined(STM32F0xx)
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56
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-// For STM32F103ZET6/STM32F103VET6/STM32F0xx
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-// SRAM (0x20000000 - 0x20010000) (64kb)
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58
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-// FLASH (0x00000000 - 0x00080000) (512kb)
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-//
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-#define START_SRAM_ADDR 0x20000000
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-#define END_SRAM_ADDR 0x20010000
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-#define START_FLASH_ADDR 0x00000000
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-#define END_FLASH_ADDR 0x00080000
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-#endif
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65
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-
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-#if defined(STM32F4) || defined(STM32F4xx)
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-// For STM32F407VET
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-// SRAM (0x20000000 - 0x20030000) (192kb)
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-// FLASH (0x08000000 - 0x08080000) (512kb)
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-//
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-#define START_SRAM_ADDR 0x20000000
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-#define END_SRAM_ADDR 0x20030000
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-#define START_FLASH_ADDR 0x08000000
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-#define END_FLASH_ADDR 0x08080000
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-#endif
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-
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-#if MB(THE_BORG)
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-// For STM32F765 in BORG
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-// SRAM (0x20000000 - 0x20080000) (512kb)
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80
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-// FLASH (0x08000000 - 0x08100000) (1024kb)
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-//
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-#define START_SRAM_ADDR 0x20000000
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-#define END_SRAM_ADDR 0x20080000
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84
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-#define START_FLASH_ADDR 0x08000000
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-#define END_FLASH_ADDR 0x08100000
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-#endif
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24
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+ // For DUE, valid address ranges are
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25
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+ // SRAM (0x20070000 - 0x20088000) (96kb)
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+ // FLASH (0x00080000 - 0x00100000) (512kb)
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+ //
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+ #define START_SRAM_ADDR 0x20070000
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+ #define END_SRAM_ADDR 0x20088000
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+ #define START_FLASH_ADDR 0x00080000
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+ #define END_FLASH_ADDR 0x00100000
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+
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+#elif defined(TARGET_LPC1768)
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+
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+ // For LPC1769:
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+ // SRAM (0x10000000 - 0x10008000) (32kb)
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+ // FLASH (0x00000000 - 0x00080000) (512kb)
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+ //
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+ #define START_SRAM_ADDR 0x10000000
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+ #define END_SRAM_ADDR 0x10008000
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+ #define START_FLASH_ADDR 0x00000000
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+ #define END_FLASH_ADDR 0x00080000
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+
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+#elif 0
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+
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+ // For STM32F103CBT6
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+ // SRAM (0x20000000 - 0x20005000) (20kb)
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48
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+ // FLASH (0x00000000 - 0x00020000) (128kb)
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+ //
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+ #define START_SRAM_ADDR 0x20000000
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+ #define END_SRAM_ADDR 0x20005000
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+ #define START_FLASH_ADDR 0x00000000
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+ #define END_FLASH_ADDR 0x00020000
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+
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+#elif defined(__STM32F1__) || defined(STM32F1xx) || defined(STM32F0xx)
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+
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57
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+ // For STM32F103ZET6/STM32F103VET6/STM32F0xx
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58
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+ // SRAM (0x20000000 - 0x20010000) (64kb)
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59
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+ // FLASH (0x00000000 - 0x00080000) (512kb)
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+ //
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+ #define START_SRAM_ADDR 0x20000000
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+ #define END_SRAM_ADDR 0x20010000
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+ #define START_FLASH_ADDR 0x00000000
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+ #define END_FLASH_ADDR 0x00080000
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+
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+#elif defined(STM32F4) || defined(STM32F4xx)
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+
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68
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+ // For STM32F407VET
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69
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+ // SRAM (0x20000000 - 0x20030000) (192kb)
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70
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+ // FLASH (0x08000000 - 0x08080000) (512kb)
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+ //
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+ #define START_SRAM_ADDR 0x20000000
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73
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+ #define END_SRAM_ADDR 0x20030000
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+ #define START_FLASH_ADDR 0x08000000
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+ #define END_FLASH_ADDR 0x08080000
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+
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+#elif MB(THE_BORG)
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+
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79
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+ // For STM32F765 in BORG
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80
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+ // SRAM (0x20000000 - 0x20080000) (512kb)
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81
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+ // FLASH (0x08000000 - 0x08100000) (1024kb)
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82
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+ //
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83
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+ #define START_SRAM_ADDR 0x20000000
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84
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+ #define END_SRAM_ADDR 0x20080000
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85
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+ #define START_FLASH_ADDR 0x08000000
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86
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+ #define END_FLASH_ADDR 0x08100000
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87
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+
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88
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+#elif MB(REMRAM_V1)
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89
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+
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90
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+ // For STM32F765VI in RemRam v1
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+ // SRAM (0x20000000 - 0x20080000) (512kb)
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92
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+ // FLASH (0x08000000 - 0x08200000) (2048kb)
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+ //
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94
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+ #define START_SRAM_ADDR 0x20000000
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+ #define END_SRAM_ADDR 0x20080000
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96
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+ #define START_FLASH_ADDR 0x08000000
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+ #define END_FLASH_ADDR 0x08200000
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+
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99
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+#elif defined(__MK20DX256__)
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+
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101
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+ // For MK20DX256 in TEENSY 3.1 or TEENSY 3.2
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102
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+ // SRAM (0x1FFF8000 - 0x20008000) (64kb)
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103
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+ // FLASH (0x00000000 - 0x00040000) (256kb)
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+ //
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+ #define START_SRAM_ADDR 0x1FFF8000
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+ #define END_SRAM_ADDR 0x20008000
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+ #define START_FLASH_ADDR 0x00000000
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+ #define END_FLASH_ADDR 0x00040000
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+
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+#elif defined(__MK64FX512__)
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111
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+
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112
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+ // For MK64FX512 in TEENSY 3.5
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+ // SRAM (0x1FFF0000 - 0x20020000) (192kb)
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114
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+ // FLASH (0x00000000 - 0x00080000) (512kb)
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+ //
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+ #define START_SRAM_ADDR 0x1FFF0000
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117
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+ #define END_SRAM_ADDR 0x20020000
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+ #define START_FLASH_ADDR 0x00000000
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+ #define END_FLASH_ADDR 0x00080000
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+
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121
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+#elif defined(__MK66FX1M0__)
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122
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+
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123
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+ // For MK66FX1M0 in TEENSY 3.6
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124
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+ // SRAM (0x1FFF0000 - 0x20030000) (256kb)
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125
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+ // FLASH (0x00000000 - 0x00140000) (1.25Mb)
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+ //
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127
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+ #define START_SRAM_ADDR 0x1FFF0000
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128
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+ #define END_SRAM_ADDR 0x20030000
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+ #define START_FLASH_ADDR 0x00000000
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+ #define END_FLASH_ADDR 0x00140000
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+
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+#elif defined(__SAMD51P20A__)
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+
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+ // For SAMD51x20, valid address ranges are
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135
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+ // SRAM (0x20000000 - 0x20040000) (256kb)
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136
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+ // FLASH (0x00000000 - 0x00100000) (1024kb)
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137
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+ //
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138
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+ #define START_SRAM_ADDR 0x20000000
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139
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+ #define END_SRAM_ADDR 0x20040000
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+ #define START_FLASH_ADDR 0x00000000
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141
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+ #define END_FLASH_ADDR 0x00100000
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87
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142
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88
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-#if MB(REMRAM_V1)
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89
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-// For STM32F765VI in RemRam v1
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90
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-// SRAM (0x20000000 - 0x20080000) (512kb)
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91
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-// FLASH (0x08000000 - 0x08200000) (2048kb)
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92
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-//
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93
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-#define START_SRAM_ADDR 0x20000000
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-#define END_SRAM_ADDR 0x20080000
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-#define START_FLASH_ADDR 0x08000000
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96
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-#define END_FLASH_ADDR 0x08200000
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-#endif
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98
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-
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99
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-#ifdef __MK20DX256__
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100
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-// For MK20DX256 in TEENSY 3.1 or TEENSY 3.2
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101
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-// SRAM (0x1FFF8000 - 0x20008000) (64kb)
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102
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-// FLASH (0x00000000 - 0x00040000) (256kb)
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103
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-//
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104
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-#define START_SRAM_ADDR 0x1FFF8000
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105
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-#define END_SRAM_ADDR 0x20008000
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106
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-#define START_FLASH_ADDR 0x00000000
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107
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-#define END_FLASH_ADDR 0x00040000
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108
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-#endif
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109
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-
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110
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-#ifdef __MK64FX512__
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111
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-// For MK64FX512 in TEENSY 3.5
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112
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-// SRAM (0x1FFF0000 - 0x20020000) (192kb)
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113
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-// FLASH (0x00000000 - 0x00080000) (512kb)
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114
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-//
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115
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-#define START_SRAM_ADDR 0x1FFF0000
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116
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-#define END_SRAM_ADDR 0x20020000
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117
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-#define START_FLASH_ADDR 0x00000000
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118
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-#define END_FLASH_ADDR 0x00080000
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119
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-#endif
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120
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-
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121
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-#ifdef __MK66FX1M0__
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122
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-// For MK66FX1M0 in TEENSY 3.6
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123
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-// SRAM (0x1FFF0000 - 0x20030000) (256kb)
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124
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-// FLASH (0x00000000 - 0x00140000) (1.25Mb)
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125
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-//
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126
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-#define START_SRAM_ADDR 0x1FFF0000
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127
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-#define END_SRAM_ADDR 0x20030000
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128
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-#define START_FLASH_ADDR 0x00000000
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129
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-#define END_FLASH_ADDR 0x00140000
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130
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-#endif
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131
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-
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132
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-#ifdef __SAMD51P20A__
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133
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-// For SAMD51x20, valid address ranges are
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134
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-// SRAM (0x20000000 - 0x20040000) (256kb)
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135
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-// FLASH (0x00000000 - 0x00100000) (1024kb)
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136
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-//
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137
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-#define START_SRAM_ADDR 0x20000000
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138
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-#define END_SRAM_ADDR 0x20040000
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139
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-#define START_FLASH_ADDR 0x00000000
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140
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-#define END_FLASH_ADDR 0x00100000
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141
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143
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#endif
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142
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144
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143
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145
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static bool validate_addr(uint32_t addr) {
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@@ -177,4 +179,4 @@ bool UnwReadB(const uint32_t a, uint8_t *v) {
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177
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179
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return true;
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180
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}
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179
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181
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180
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-#endif
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182
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+#endif // __arm__ || __thumb__
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