Przeglądaj źródła

Fix STM32F1 SPI warning (gcc 8.2.1) (#15104)

Tanguy Pruvot 5 lat temu
rodzic
commit
c014f8dc78
1 zmienionych plików z 87 dodań i 90 usunięć
  1. 87
    90
      Marlin/src/HAL/HAL_STM32F1/SPI.cpp

+ 87
- 90
Marlin/src/HAL/HAL_STM32F1/SPI.cpp Wyświetl plik

47
   #warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
47
   #warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
48
 #endif
48
 #endif
49
 
49
 
50
-struct spi_pins {
51
-  uint8_t nss;
52
-  uint8_t sck;
53
-  uint8_t miso;
54
-  uint8_t mosi;
55
-};
50
+struct spi_pins { uint8_t nss, sck, miso, mosi; };
56
 
51
 
57
 static const spi_pins* dev_to_spi_pins(spi_dev *dev);
52
 static const spi_pins* dev_to_spi_pins(spi_dev *dev);
58
 static void configure_gpios(spi_dev *dev, bool as_master);
53
 static void configure_gpios(spi_dev *dev, bool as_master);
64
 
59
 
65
 static const spi_pins board_spi_pins[] __FLASH__ = {
60
 static const spi_pins board_spi_pins[] __FLASH__ = {
66
   #if BOARD_NR_SPI >= 1
61
   #if BOARD_NR_SPI >= 1
67
-  { BOARD_SPI1_NSS_PIN,
68
-    BOARD_SPI1_SCK_PIN,
69
-    BOARD_SPI1_MISO_PIN,
70
-    BOARD_SPI1_MOSI_PIN },
62
+    { BOARD_SPI1_NSS_PIN,
63
+      BOARD_SPI1_SCK_PIN,
64
+      BOARD_SPI1_MISO_PIN,
65
+      BOARD_SPI1_MOSI_PIN },
71
   #endif
66
   #endif
72
   #if BOARD_NR_SPI >= 2
67
   #if BOARD_NR_SPI >= 2
73
-  { BOARD_SPI2_NSS_PIN,
74
-    BOARD_SPI2_SCK_PIN,
75
-    BOARD_SPI2_MISO_PIN,
76
-    BOARD_SPI2_MOSI_PIN },
68
+    { BOARD_SPI2_NSS_PIN,
69
+      BOARD_SPI2_SCK_PIN,
70
+      BOARD_SPI2_MISO_PIN,
71
+      BOARD_SPI2_MOSI_PIN },
77
   #endif
72
   #endif
78
   #if BOARD_NR_SPI >= 3
73
   #if BOARD_NR_SPI >= 3
79
-  { BOARD_SPI3_NSS_PIN,
80
-    BOARD_SPI3_SCK_PIN,
81
-    BOARD_SPI3_MISO_PIN,
82
-    BOARD_SPI3_MOSI_PIN },
74
+    { BOARD_SPI3_NSS_PIN,
75
+      BOARD_SPI3_SCK_PIN,
76
+      BOARD_SPI3_MISO_PIN,
77
+      BOARD_SPI3_MOSI_PIN },
83
   #endif
78
   #endif
84
 };
79
 };
85
 
80
 
86
 #if BOARD_NR_SPI >= 1
81
 #if BOARD_NR_SPI >= 1
87
-  static void (*_spi1_this);
82
+  static void *_spi1_this;
88
 #endif
83
 #endif
89
 #if BOARD_NR_SPI >= 2
84
 #if BOARD_NR_SPI >= 2
90
-  static void (*_spi2_this);
85
+  static void *_spi2_this;
91
 #endif
86
 #endif
92
 #if BOARD_NR_SPI >= 3
87
 #if BOARD_NR_SPI >= 3
93
-  static void (*_spi3_this);
88
+  static void *_spi3_this;
94
 #endif
89
 #endif
95
 
90
 
96
 /**
91
 /**
97
  * Constructor
92
  * Constructor
98
  */
93
  */
99
 SPIClass::SPIClass(uint32_t spi_num) {
94
 SPIClass::SPIClass(uint32_t spi_num) {
100
-  _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
95
+  _currentSetting = &_settings[spi_num - 1];  // SPI channels are called 1 2 and 3 but the array is zero indexed
101
 
96
 
102
   switch (spi_num) {
97
   switch (spi_num) {
103
     #if BOARD_NR_SPI >= 1
98
     #if BOARD_NR_SPI >= 1
149
   _currentSetting->state = SPI_STATE_IDLE;
144
   _currentSetting->state = SPI_STATE_IDLE;
150
 }
145
 }
151
 
146
 
152
-/*
147
+/**
153
  * Set up/tear down
148
  * Set up/tear down
154
  */
149
  */
155
 void SPIClass::updateSettings() {
150
 void SPIClass::updateSettings() {
175
 }
170
 }
176
 
171
 
177
 void SPIClass::end() {
172
 void SPIClass::end() {
178
-  if (!spi_is_enabled(_currentSetting->spi_d))
179
-    return;
173
+  if (!spi_is_enabled(_currentSetting->spi_d)) return;
180
 
174
 
181
   // Follows RM0008's sequence for disabling a SPI in master/slave
175
   // Follows RM0008's sequence for disabling a SPI in master/slave
182
   // full duplex mode.
176
   // full duplex mode.
184
     // FIXME [0.1.0] remove this once you have an interrupt based driver
178
     // FIXME [0.1.0] remove this once you have an interrupt based driver
185
     volatile uint16_t rx __attribute__((unused)) = spi_rx_reg(_currentSetting->spi_d);
179
     volatile uint16_t rx __attribute__((unused)) = spi_rx_reg(_currentSetting->spi_d);
186
   }
180
   }
187
-  while (!spi_is_tx_empty(_currentSetting->spi_d)) {};
188
-  while (spi_is_busy(_currentSetting->spi_d)) {};
181
+  while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ }
182
+  while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ }
189
 
183
 
190
   spi_peripheral_disable(_currentSetting->spi_d);
184
   spi_peripheral_disable(_currentSetting->spi_d);
191
   // added for DMA callbacks.
185
   // added for DMA callbacks.
207
   _currentSetting->spi_d->regs->CR1 = cr1;
201
   _currentSetting->spi_d->regs->CR1 = cr1;
208
 }
202
 }
209
 
203
 
210
-/*  Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
211
-* Input parameter should be SPI_CR1_DFF set to 0 or 1 on a 32bit word.
212
-*
213
-*/
204
+/**
205
+ * Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
206
+ * Input parameter should be SPI_CR1_DFF set to 0 or 1 on a 32bit word.
207
+ */
214
 void SPIClass::setDataSize(uint32_t datasize) {
208
 void SPIClass::setDataSize(uint32_t datasize) {
215
   _currentSetting->dataSize = datasize;
209
   _currentSetting->dataSize = datasize;
216
   uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
210
   uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
220
 }
214
 }
221
 
215
 
222
 void SPIClass::setDataMode(uint8_t dataMode) {
216
 void SPIClass::setDataMode(uint8_t dataMode) {
223
-  /* Notes:
224
-  As far as I can tell, the AVR numbers for dataMode appear to match the numbers required by the STM32
217
+  /*
218
+  Notes:
219
+  As far as we know the AVR numbers for dataMode match the numbers required by the STM32.
225
   From the AVR doc http://www.atmel.com/images/doc2585.pdf section 2.4
220
   From the AVR doc http://www.atmel.com/images/doc2585.pdf section 2.4
221
+
226
   SPI Mode  CPOL  CPHA  Shift SCK-edge  Capture SCK-edge
222
   SPI Mode  CPOL  CPHA  Shift SCK-edge  Capture SCK-edge
227
   0       0     0     Falling     Rising
223
   0       0     0     Falling     Rising
228
   1       0     1     Rising      Falling
224
   1       0     1     Rising      Falling
265
 
261
 
266
 void SPIClass::endTransaction() { }
262
 void SPIClass::endTransaction() { }
267
 
263
 
268
-
269
-/*
264
+/**
270
  * I/O
265
  * I/O
271
  */
266
  */
272
 
267
 
273
 uint16_t SPIClass::read() {
268
 uint16_t SPIClass::read() {
274
-  while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
269
+  while (!spi_is_rx_nonempty(_currentSetting->spi_d)) { /* nada */ }
275
   return (uint16)spi_rx_reg(_currentSetting->spi_d);
270
   return (uint16)spi_rx_reg(_currentSetting->spi_d);
276
 }
271
 }
277
 
272
 
282
   // start sequence: write byte 0
277
   // start sequence: write byte 0
283
   regs->DR = 0x00FF;            // write the first byte
278
   regs->DR = 0x00FF;            // write the first byte
284
   // main loop
279
   // main loop
285
-  while ( (--len) ) {
286
-    while( !(regs->SR & SPI_SR_TXE) ); // wait for TXE flag
280
+  while (--len) {
281
+    while(!(regs->SR & SPI_SR_TXE)) { /* nada */ } // wait for TXE flag
287
     noInterrupts();    // go atomic level - avoid interrupts to surely get the previously received data
282
     noInterrupts();    // go atomic level - avoid interrupts to surely get the previously received data
288
     regs->DR = 0x00FF; // write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
283
     regs->DR = 0x00FF; // write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
289
-    while ( !(regs->SR & SPI_SR_RXNE) ); // wait till data is available in the DR register
284
+    while (!(regs->SR & SPI_SR_RXNE)) { /* nada */ } // wait till data is available in the DR register
290
     *buf++ = (uint8)(regs->DR); // read and store the received byte. This clears the RXNE flag.
285
     *buf++ = (uint8)(regs->DR); // read and store the received byte. This clears the RXNE flag.
291
     interrupts();      // let systick do its job
286
     interrupts();      // let systick do its job
292
   }
287
   }
293
   // read remaining last byte
288
   // read remaining last byte
294
-  while ( !(regs->SR & SPI_SR_RXNE) ) {} // wait till data is available in the Rx register
289
+  while (!(regs->SR & SPI_SR_RXNE)) { /* nada */ } // wait till data is available in the Rx register
295
   *buf++ = (uint8)(regs->DR);  // read and store the received byte
290
   *buf++ = (uint8)(regs->DR);  // read and store the received byte
296
 }
291
 }
297
 
292
 
302
    * This almost doubles the speed of this function.
297
    * This almost doubles the speed of this function.
303
    */
298
    */
304
   spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
299
   spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
305
-  while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
306
-  while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
300
+  while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
301
+  while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
307
 }
302
 }
308
 
303
 
309
 void SPIClass::write16(uint16_t data) {
304
 void SPIClass::write16(uint16_t data) {
310
   // Added by stevestrong: write two consecutive bytes in 8 bit mode (DFF=0)
305
   // Added by stevestrong: write two consecutive bytes in 8 bit mode (DFF=0)
311
   spi_tx_reg(_currentSetting->spi_d, data>>8); // write high byte
306
   spi_tx_reg(_currentSetting->spi_d, data>>8); // write high byte
312
-  while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1
307
+  while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // Wait until TXE=1
313
   spi_tx_reg(_currentSetting->spi_d, data); // write low byte
308
   spi_tx_reg(_currentSetting->spi_d, data); // write low byte
314
-  while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1
315
-  while (spi_is_busy(_currentSetting->spi_d) != 0); // wait until BSY=0
309
+  while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // Wait until TXE=1
310
+  while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // wait until BSY=0
316
 }
311
 }
317
 
312
 
318
 void SPIClass::write(uint16_t data, uint32_t n) {
313
 void SPIClass::write(uint16_t data, uint32_t n) {
319
   // Added by stevstrong: Repeatedly send same data by the specified number of times
314
   // Added by stevstrong: Repeatedly send same data by the specified number of times
320
   spi_reg_map * regs = _currentSetting->spi_d->regs;
315
   spi_reg_map * regs = _currentSetting->spi_d->regs;
321
-  while ( (n--)>0 ) {
316
+  while (n--) {
322
     regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
317
     regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
323
-    while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
318
+    while (!(regs->SR & SPI_SR_TXE)) { /* nada */ } // wait till Tx empty
324
   }
319
   }
325
-  while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning
320
+  while (regs->SR & SPI_SR_BSY) { /* nada */ } // wait until BSY=0 before returning
326
 }
321
 }
327
 
322
 
328
 void SPIClass::write(const void *data, uint32_t length) {
323
 void SPIClass::write(const void *data, uint32_t length) {
329
   spi_dev * spi_d = _currentSetting->spi_d;
324
   spi_dev * spi_d = _currentSetting->spi_d;
330
   spi_tx(spi_d, data, length); // data can be array of bytes or words
325
   spi_tx(spi_d, data, length); // data can be array of bytes or words
331
-  while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
332
-  while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
326
+  while (!spi_is_tx_empty(spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
327
+  while (spi_is_busy(spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
333
 }
328
 }
334
 
329
 
335
 uint8_t SPIClass::transfer(uint8_t byte) const {
330
 uint8_t SPIClass::transfer(uint8_t byte) const {
336
   spi_dev * spi_d = _currentSetting->spi_d;
331
   spi_dev * spi_d = _currentSetting->spi_d;
337
   spi_rx_reg(spi_d); // read any previous data
332
   spi_rx_reg(spi_d); // read any previous data
338
   spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
333
   spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
339
-  while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
340
-  while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
334
+  while (!spi_is_tx_empty(spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
335
+  while (spi_is_busy(spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
341
   return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
336
   return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
342
 }
337
 }
343
 
338
 
345
   // Modified by stevestrong: write & read two consecutive bytes in 8 bit mode (DFF=0)
340
   // Modified by stevestrong: write & read two consecutive bytes in 8 bit mode (DFF=0)
346
   // This is more effective than two distinct byte transfers
341
   // This is more effective than two distinct byte transfers
347
   spi_dev * spi_d = _currentSetting->spi_d;
342
   spi_dev * spi_d = _currentSetting->spi_d;
348
-  spi_rx_reg(spi_d);                   // read any previous data
349
-  spi_tx_reg(spi_d, data>>8);          // write high byte
350
-  while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1
351
-  while (spi_is_busy(spi_d) != 0);     // wait until BSY=0
352
-  uint16_t ret = spi_rx_reg(spi_d)<<8; // read and shift high byte
353
-  spi_tx_reg(spi_d, data);             // write low byte
354
-  while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1
355
-  while (spi_is_busy(spi_d) != 0);     // wait until BSY=0
356
-  ret += spi_rx_reg(spi_d);            // read low byte
343
+  spi_rx_reg(spi_d);                              // read any previous data
344
+  spi_tx_reg(spi_d, data>>8);                     // write high byte
345
+  while (!spi_is_tx_empty(spi_d)) { /* nada */ }  // wait until TXE=1
346
+  while (spi_is_busy(spi_d)) { /* nada */ }       // wait until BSY=0
347
+  uint16_t ret = spi_rx_reg(spi_d)<<8;            // read and shift high byte
348
+  spi_tx_reg(spi_d, data);                        // write low byte
349
+  while (!spi_is_tx_empty(spi_d)) { /* nada */ }  // wait until TXE=1
350
+  while (spi_is_busy(spi_d)) { /* nada */ }       // wait until BSY=0
351
+  ret += spi_rx_reg(spi_d);                       // read low byte
357
   return ret;
352
   return ret;
358
 }
353
 }
359
 
354
 
360
-/*  Roger Clark and Victor Perez, 2015
361
-* Performs a DMA SPI transfer with at least a receive buffer.
362
-* If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer.
363
-* On exit TX buffer is not modified, and RX buffer cotains the received data.
364
-* Still in progress.
365
-*/
355
+/**
356
+ * Roger Clark and Victor Perez, 2015
357
+ * Performs a DMA SPI transfer with at least a receive buffer.
358
+ * If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer.
359
+ * On exit TX buffer is not modified, and RX buffer cotains the received data.
360
+ * Still in progress.
361
+ */
366
 void SPIClass::dmaTransferSet(const void *transmitBuf, void *receiveBuf) {
362
 void SPIClass::dmaTransferSet(const void *transmitBuf, void *receiveBuf) {
367
   dma_init(_currentSetting->spiDmaDev);
363
   dma_init(_currentSetting->spiDmaDev);
368
   //spi_rx_dma_enable(_currentSetting->spi_d);
364
   //spi_rx_dma_enable(_currentSetting->spi_d);
399
   //uint32_t m = millis();
395
   //uint32_t m = millis();
400
   uint8_t b = 0;
396
   uint8_t b = 0;
401
   uint32_t m = millis();
397
   uint32_t m = millis();
402
-  while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1) == 0) {
403
-    //Avoid interrupts and just loop waiting for the flag to be set.
398
+  while (!(dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)) {
399
+    // Avoid interrupts and just loop waiting for the flag to be set.
404
     if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
400
     if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
405
   }
401
   }
406
 
402
 
407
-  while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
408
-  while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
403
+  while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
404
+  while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
409
   spi_tx_dma_disable(_currentSetting->spi_d);
405
   spi_tx_dma_disable(_currentSetting->spi_d);
410
   spi_rx_dma_disable(_currentSetting->spi_d);
406
   spi_rx_dma_disable(_currentSetting->spi_d);
411
   dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
407
   dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
416
   return b;
412
   return b;
417
 }
413
 }
418
 
414
 
419
-/* Roger Clark and Victor Perez, 2015
415
+/**
416
+ * Roger Clark and Victor Perez, 2015
420
  * Performs a DMA SPI transfer with at least a receive buffer.
417
  * Performs a DMA SPI transfer with at least a receive buffer.
421
  * If a TX buffer is not provided, FF is sent over and over for the length of the transfer.
418
  * If a TX buffer is not provided, FF is sent over and over for the length of the transfer.
422
  * On exit TX buffer is not modified, and RX buffer contains the received data.
419
  * On exit TX buffer is not modified, and RX buffer contains the received data.
427
   return dmaTransferRepeat(length);
424
   return dmaTransferRepeat(length);
428
 }
425
 }
429
 
426
 
430
-/* Roger Clark and Victor Perez, 2015
427
+/**
428
+ * Roger Clark and Victor Perez, 2015
431
  * Performs a DMA SPI send using a TX buffer.
429
  * Performs a DMA SPI send using a TX buffer.
432
  * On exit TX buffer is not modified.
430
  * On exit TX buffer is not modified.
433
  * Still in progress.
431
  * Still in progress.
448
   dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
446
   dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
449
   dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
447
   dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
450
   _currentSetting->state = SPI_STATE_TRANSMIT;
448
   _currentSetting->state = SPI_STATE_TRANSMIT;
451
-  dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
449
+  dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);   // enable transmit
452
   spi_tx_dma_enable(_currentSetting->spi_d);
450
   spi_tx_dma_enable(_currentSetting->spi_d);
453
-  if (_currentSetting->transmitCallback)
454
-    return 0;
451
+  if (_currentSetting->transmitCallback) return 0;
455
 
452
 
456
   uint32_t m = millis();
453
   uint32_t m = millis();
457
   uint8_t b = 0;
454
   uint8_t b = 0;
458
-  while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
459
-    //Avoid interrupts and just loop waiting for the flag to be set.
455
+  while (!(dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)) {
456
+    // Avoid interrupts and just loop waiting for the flag to be set.
460
     if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
457
     if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
461
   }
458
   }
462
-  while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
463
-  while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
459
+  while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
460
+  while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
464
   spi_tx_dma_disable(_currentSetting->spi_d);
461
   spi_tx_dma_disable(_currentSetting->spi_d);
465
   dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
462
   dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
466
   dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
463
   dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
478
 
475
 
479
   if (_currentSetting->state != SPI_STATE_READY) {
476
   if (_currentSetting->state != SPI_STATE_READY) {
480
     uint32_t m = millis();
477
     uint32_t m = millis();
481
-    while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
478
+    while (!(dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)) {
482
       //Avoid interrupts and just loop waiting for the flag to be set.
479
       //Avoid interrupts and just loop waiting for the flag to be set.
483
       //delayMicroseconds(10);
480
       //delayMicroseconds(10);
484
       if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
481
       if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
485
     }
482
     }
486
 
483
 
487
-    while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
488
-    while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
484
+    while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
485
+    while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // "... and then wait until BSY=0 before disabling the SPI."
489
     spi_tx_dma_disable(_currentSetting->spi_d);
486
     spi_tx_dma_disable(_currentSetting->spi_d);
490
     dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
487
     dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
491
     _currentSetting->state = SPI_STATE_READY;
488
     _currentSetting->state = SPI_STATE_READY;
575
  * during the initial setup and only set the callback to EventCallback if they are set.
572
  * during the initial setup and only set the callback to EventCallback if they are set.
576
  */
573
  */
577
 void SPIClass::EventCallback() {
574
 void SPIClass::EventCallback() {
578
-  while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
579
-  while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0"
575
+  while (!spi_is_tx_empty(_currentSetting->spi_d)) { /* nada */ } // "5. Wait until TXE=1 ..."
576
+  while (spi_is_busy(_currentSetting->spi_d)) { /* nada */ } // "... and then wait until BSY=0"
580
   switch (_currentSetting->state) {
577
   switch (_currentSetting->state) {
581
   case SPI_STATE_TRANSFER:
578
   case SPI_STATE_TRANSFER:
582
-    while (spi_is_rx_nonempty(_currentSetting->spi_d));
579
+    while (spi_is_rx_nonempty(_currentSetting->spi_d)) { /* nada */ }
583
     _currentSetting->state = SPI_STATE_READY;
580
     _currentSetting->state = SPI_STATE_READY;
584
     spi_tx_dma_disable(_currentSetting->spi_d);
581
     spi_tx_dma_disable(_currentSetting->spi_d);
585
     spi_rx_dma_disable(_currentSetting->spi_d);
582
     spi_rx_dma_disable(_currentSetting->spi_d);
718
   SPI_BAUD_PCLK_DIV_256,
715
   SPI_BAUD_PCLK_DIV_256,
719
 };
716
 };
720
 
717
 
721
-/*
722
-* Note: This assumes you're on a LeafLabs-style board
723
-* (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
724
-*/
718
+/**
719
+ * Note: This assumes you're on a LeafLabs-style board
720
+ * (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
721
+ */
725
 static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
722
 static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
726
   uint32_t clock = 0;
723
   uint32_t clock = 0;
727
   switch (rcc_dev_clk(dev->clk_id)) {
724
   switch (rcc_dev_clk(dev->clk_id)) {

Ładowanie…
Anuluj
Zapisz