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@@ -153,11 +153,13 @@ void LPC1768_PWM_update_map_MR(void) {
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153
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153
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map_MR[0] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P1_18_PWM_channel) ? 1 : 0), P1_18, &LPC_PWM1->MR1, 0, 0, 0 };
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154
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154
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map_MR[1] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P1_20_PWM_channel) ? 1 : 0), P1_20, &LPC_PWM1->MR2, 0, 0, 0 };
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155
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155
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map_MR[2] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P1_21_PWM_channel) ? 1 : 0), P1_21, &LPC_PWM1->MR3, 0, 0, 0 };
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156
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- #if MOTHERBOARD == BOARD_MKS_SBASE
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157
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- map_MR[3] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P1_23_PWM_channel) ? 1 : 0), P1_23, &LPC_PWM1->MR4, 0, 0, 0 };
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158
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- #else
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159
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- map_MR[3] = { 0, 0, P_NC, &LPC_PWM1->MR4, 0, 0, 0 };
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160
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- #endif
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156
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+ map_MR[3] = {
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157
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+ #if MB(MKS_SBASE)
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158
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+ 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P1_23_PWM_channel) ? 1 : 0), P1_23, &LPC_PWM1->MR4, 0, 0, 0
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159
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+ #else
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160
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+ 0, 0, P_NC, &LPC_PWM1->MR4, 0, 0, 0
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161
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+ #endif
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162
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+ };
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161
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163
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map_MR[4] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P2_04_PWM_channel) ? 1 : 0), P2_04, &LPC_PWM1->MR5, 0, 0, 0 };
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162
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164
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map_MR[5] = { 0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + P2_05_PWM_channel) ? 1 : 0), P2_05, &LPC_PWM1->MR6, 0, 0, 0 };
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163
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165
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}
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@@ -212,7 +214,7 @@ void LPC1768_PWM_init(void) {
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212
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214
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LPC_PWM1->MR0 = LPC_PWM1_MR0; // TC resets every 19,999 + 1 cycles - sets PWM cycle(Ton+Toff) to 20 mS
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213
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215
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// MR0 must be set before TCR enables the PWM
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214
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216
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LPC_PWM1->TCR = _BV(SBIT_CNTEN) | _BV(SBIT_CNTRST) | _BV(SBIT_PWMEN); // Enable counters, reset counters, set mode to PWM
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215
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- LPC_PWM1->TCR &= ~(_BV(SBIT_CNTRST)); // Take counters out of reset
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217
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+ CBI(LPC_PWM1->TCR, SBIT_CNTRST); // Take counters out of reset
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216
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218
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LPC_PWM1->PR = LPC_PWM1_PR;
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217
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219
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LPC_PWM1->MCR = _BV(SBIT_PWMMR0R) | _BV(0); // Reset TC if it matches MR0, disable all interrupts except for MR0
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218
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220
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LPC_PWM1->CTCR = 0; // Disable counter mode (enable PWM mode)
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@@ -279,47 +281,47 @@ bool LPC1768_PWM_detach_pin(pin_t pin) {
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279
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281
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280
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282
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// OK to make these changes before the MR0 interrupt
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281
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283
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switch(pin) {
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282
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- case P1_23: // MKS Sbase Servo 0, PWM1 channel 4 (J3-8 PWM1.4)
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283
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- LPC_PWM1->PCR &= ~(_BV(8 + P1_23_PWM_channel)); // disable PWM1 module control of this pin
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284
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+ case P1_23: // MKS Sbase Servo 0, PWM1 channel 4 (J3-8 PWM1.4)
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285
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+ CBI(LPC_PWM1->PCR, 8 + P1_23_PWM_channel); // disable PWM1 module control of this pin
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284
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286
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map_MR[P1_23_PWM_channel - 1].PCR_bit = 0;
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285
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- LPC_PINCON->PINSEL3 &= ~(0x3 << 14); // return pin to general purpose I/O
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287
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+ LPC_PINCON->PINSEL3 &= ~(0x3 << 14); // return pin to general purpose I/O
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286
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288
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map_MR[P1_23_PWM_channel - 1].PINSEL_bits = 0;
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287
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- map_MR[P1_23_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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289
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+ map_MR[P1_23_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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288
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290
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break;
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289
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- case P1_20: // Servo 0, PWM1 channel 2 (Pin 11 P1.20 PWM1.2)
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290
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- LPC_PWM1->PCR &= ~(_BV(8 + P1_20_PWM_channel)); // disable PWM1 module control of this pin
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291
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+ case P1_20: // Servo 0, PWM1 channel 2 (Pin 11 P1.20 PWM1.2)
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292
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+ CBI(LPC_PWM1->PCR, 8 + P1_20_PWM_channel); // disable PWM1 module control of this pin
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291
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293
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map_MR[P1_20_PWM_channel - 1].PCR_bit = 0;
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292
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- LPC_PINCON->PINSEL3 &= ~(0x3 << 8); // return pin to general purpose I/O
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294
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+ LPC_PINCON->PINSEL3 &= ~(0x3 << 8); // return pin to general purpose I/O
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293
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295
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map_MR[P1_20_PWM_channel - 1].PINSEL_bits = 0;
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294
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- map_MR[P1_20_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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296
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+ map_MR[P1_20_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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295
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297
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break;
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296
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- case P1_21: // Servo 1, PWM1 channel 3 (Pin 6 P1.21 PWM1.3)
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297
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- LPC_PWM1->PCR &= ~(_BV(8 + P1_21_PWM_channel)); // disable PWM1 module control of this pin
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298
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+ case P1_21: // Servo 1, PWM1 channel 3 (Pin 6 P1.21 PWM1.3)
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299
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+ CBI(LPC_PWM1->PCR, 8 + P1_21_PWM_channel); // disable PWM1 module control of this pin
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298
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300
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map_MR[P1_21_PWM_channel - 1].PCR_bit = 0;
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299
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- LPC_PINCON->PINSEL3 &= ~(0x3 << 10); // return pin to general purpose I/O
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301
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+ LPC_PINCON->PINSEL3 &= ~(0x3 << 10); // return pin to general purpose I/O
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300
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302
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map_MR[P1_21_PWM_channel - 1].PINSEL_bits = 0;
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301
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- map_MR[P1_21_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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303
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+ map_MR[P1_21_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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302
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304
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break;
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303
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- case P1_18: // Servo 3, PWM1 channel 1 (Pin 4 P1.18 PWM1.1)
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304
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- LPC_PWM1->PCR &= ~(_BV(8 + P1_18_PWM_channel)); // disable PWM1 module control of this pin
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305
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+ case P1_18: // Servo 3, PWM1 channel 1 (Pin 4 P1.18 PWM1.1)
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306
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+ CBI(LPC_PWM1->PCR, 8 + P1_18_PWM_channel); // disable PWM1 module control of this pin
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305
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307
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map_MR[P1_18_PWM_channel - 1].PCR_bit = 0;
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306
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- LPC_PINCON->PINSEL3 &= ~(0x3 << 4); // return pin to general purpose I/O
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308
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+ LPC_PINCON->PINSEL3 &= ~(0x3 << 4); // return pin to general purpose I/O
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307
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309
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map_MR[P1_18_PWM_channel - 1].PINSEL_bits = 0;
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308
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- map_MR[P1_18_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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310
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+ map_MR[P1_18_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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309
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311
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break;
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310
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- case P2_04: // D9 FET, PWM1 channel 5 (Pin 9 P2_04 PWM1.5)
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311
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- LPC_PWM1->PCR &= ~(_BV(8 + P2_04_PWM_channel)); // disable PWM1 module control of this pin
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312
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+ case P2_04: // D9 FET, PWM1 channel 5 (Pin 9 P2_04 PWM1.5)
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313
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+ CBI(LPC_PWM1->PCR, 8 + P2_04_PWM_channel); // disable PWM1 module control of this pin
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312
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314
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map_MR[P2_04_PWM_channel - 1].PCR_bit = 0;
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313
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- LPC_PINCON->PINSEL4 &= ~(0x3 << 10); // return pin to general purpose I/O
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315
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+ LPC_PINCON->PINSEL4 &= ~(0x3 << 10); // return pin to general purpose I/O
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314
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316
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map_MR[P2_04_PWM_channel - 1].PINSEL_bits = 0;
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315
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- map_MR[P2_04_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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317
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+ map_MR[P2_04_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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316
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318
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break;
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317
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- case P2_05: // D10 FET, PWM1 channel 6 (Pin 10 P2_05 PWM1.6)
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318
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- LPC_PWM1->PCR &= ~(_BV(8 + P2_05_PWM_channel)); // disable PWM1 module control of this pin
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319
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+ case P2_05: // D10 FET, PWM1 channel 6 (Pin 10 P2_05 PWM1.6)
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320
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+ CBI(LPC_PWM1->PCR, 8 + P2_05_PWM_channel); // disable PWM1 module control of this pin
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319
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321
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map_MR[P2_05_PWM_channel - 1].PCR_bit = 0;
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320
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- LPC_PINCON->PINSEL4 &= ~(0x3 << 4); // return pin to general purpose I/O
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322
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+ LPC_PINCON->PINSEL4 &= ~(0x3 << 4); // return pin to general purpose I/O
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321
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323
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map_MR[P2_05_PWM_channel - 1].PINSEL_bits = 0;
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322
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- map_MR[P2_05_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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324
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+ map_MR[P2_05_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
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323
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325
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break;
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324
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326
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default:
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325
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327
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break;
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@@ -351,35 +353,35 @@ bool LPC1768_PWM_write(pin_t pin, uint32_t value) {
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351
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353
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LPC1768_PWM_update_map_MR();
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352
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354
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353
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355
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switch(pin) {
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354
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- case P1_23: // MKS Sbase Servo 0, PWM1 channel 4 (J3-8 PWM1.4)
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355
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- map_MR[P1_23_PWM_channel - 1].PCR_bit = _BV(8 + P1_23_PWM_channel); // enable PWM1 module control of this pin
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356
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+ case P1_23: // MKS Sbase Servo 0, PWM1 channel 4 (J3-8 PWM1.4)
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357
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+ map_MR[P1_23_PWM_channel - 1].PCR_bit = _BV(8 + P1_23_PWM_channel); // enable PWM1 module control of this pin
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356
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358
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map_MR[P1_23_PWM_channel - 1].PINSEL_reg = &LPC_PINCON->PINSEL3;
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357
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- map_MR[P1_23_PWM_channel - 1].PINSEL_bits = 0x2 << 14; // ISR must do this AFTER setting PCR
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359
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+ map_MR[P1_23_PWM_channel - 1].PINSEL_bits = 0x2 << 14; // ISR must do this AFTER setting PCR
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358
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360
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break;
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359
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- case P1_20: // Servo 0, PWM1 channel 2 (Pin 11 P1.20 PWM1.2)
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360
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- map_MR[P1_20_PWM_channel - 1].PCR_bit = _BV(8 + P1_20_PWM_channel); // enable PWM1 module control of this pin
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361
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+ case P1_20: // Servo 0, PWM1 channel 2 (Pin 11 P1.20 PWM1.2)
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362
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+ map_MR[P1_20_PWM_channel - 1].PCR_bit = _BV(8 + P1_20_PWM_channel); // enable PWM1 module control of this pin
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361
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363
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map_MR[P1_20_PWM_channel - 1].PINSEL_reg = &LPC_PINCON->PINSEL3;
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362
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- map_MR[P1_20_PWM_channel - 1].PINSEL_bits = 0x2 << 8; // ISR must do this AFTER setting PCR
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364
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+ map_MR[P1_20_PWM_channel - 1].PINSEL_bits = 0x2 << 8; // ISR must do this AFTER setting PCR
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363
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365
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break;
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364
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- case P1_21: // Servo 1, PWM1 channel 3 (Pin 6 P1.21 PWM1.3)
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365
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- map_MR[P1_21_PWM_channel - 1].PCR_bit = _BV(8 + P1_21_PWM_channel); // enable PWM1 module control of this pin
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366
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+ case P1_21: // Servo 1, PWM1 channel 3 (Pin 6 P1.21 PWM1.3)
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367
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+ map_MR[P1_21_PWM_channel - 1].PCR_bit = _BV(8 + P1_21_PWM_channel); // enable PWM1 module control of this pin
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366
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368
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map_MR[P1_21_PWM_channel - 1].PINSEL_reg = &LPC_PINCON->PINSEL3;
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367
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- map_MR[P1_21_PWM_channel - 1].PINSEL_bits = 0x2 << 10; // ISR must do this AFTER setting PCR
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369
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+ map_MR[P1_21_PWM_channel - 1].PINSEL_bits = 0x2 << 10; // ISR must do this AFTER setting PCR
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368
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370
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break;
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369
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- case P1_18: // Servo 3, PWM1 channel 1 (Pin 4 P1.18 PWM1.1)
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370
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- map_MR[P1_18_PWM_channel - 1].PCR_bit = _BV(8 + P1_18_PWM_channel); // enable PWM1 module control of this pin
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371
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+ case P1_18: // Servo 3, PWM1 channel 1 (Pin 4 P1.18 PWM1.1)
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372
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+ map_MR[P1_18_PWM_channel - 1].PCR_bit = _BV(8 + P1_18_PWM_channel); // enable PWM1 module control of this pin
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371
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373
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map_MR[P1_18_PWM_channel - 1].PINSEL_reg = &LPC_PINCON->PINSEL3;
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372
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- map_MR[P1_18_PWM_channel - 1].PINSEL_bits = 0x2 << 4; // ISR must do this AFTER setting PCR
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374
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+ map_MR[P1_18_PWM_channel - 1].PINSEL_bits = 0x2 << 4; // ISR must do this AFTER setting PCR
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373
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375
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break;
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374
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- case P2_04: // D9 FET, PWM1 channel 5 (Pin 9 P2_04 PWM1.5)
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375
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- map_MR[P2_04_PWM_channel - 1].PCR_bit = _BV(8 + P2_04_PWM_channel); // enable PWM1 module control of this pin
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376
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+ case P2_04: // D9 FET, PWM1 channel 5 (Pin 9 P2_04 PWM1.5)
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377
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+ map_MR[P2_04_PWM_channel - 1].PCR_bit = _BV(8 + P2_04_PWM_channel); // enable PWM1 module control of this pin
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376
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378
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map_MR[P2_04_PWM_channel - 1].PINSEL_reg = &LPC_PINCON->PINSEL4;
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377
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- map_MR[P2_04_PWM_channel - 1].PINSEL_bits = 0x1 << 8; // ISR must do this AFTER setting PCR
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|
379
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+ map_MR[P2_04_PWM_channel - 1].PINSEL_bits = 0x1 << 8; // ISR must do this AFTER setting PCR
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378
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380
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break;
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379
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- case P2_05: // D10 FET, PWM1 channel 6 (Pin 10 P2_05 PWM1.6)
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380
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- map_MR[P2_05_PWM_channel - 1].PCR_bit = _BV(8 + P2_05_PWM_channel); // enable PWM1 module control of this pin
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381
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+ case P2_05: // D10 FET, PWM1 channel 6 (Pin 10 P2_05 PWM1.6)
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382
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+ map_MR[P2_05_PWM_channel - 1].PCR_bit = _BV(8 + P2_05_PWM_channel); // enable PWM1 module control of this pin
|
381
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383
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map_MR[P2_05_PWM_channel - 1].PINSEL_reg = &LPC_PINCON->PINSEL4;
|
382
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- map_MR[P2_05_PWM_channel - 1].PINSEL_bits = 0x1 << 10; // ISR must do this AFTER setting PCR
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|
384
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+ map_MR[P2_05_PWM_channel - 1].PINSEL_bits = 0x1 << 10; // ISR must do this AFTER setting PCR
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383
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385
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break;
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384
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386
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default: // ISR pins
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385
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387
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pinMode(pin, OUTPUT); // set pin to output
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@@ -418,11 +420,11 @@ void LPC1768_PWM_update(void) { // only called by the ISR
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418
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420
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found = false;
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419
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421
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for (uint8_t j = 0; (j < NUM_PWMS) && !found; j++) {
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420
|
422
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if ( (map_MR[j].map_PWM_PIN == ISR_table[i].pin)) {
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421
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- map_MR[j].map_PWM_INT = 1; // flag that it's already setup for direct control
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|
423
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+ map_MR[j].map_PWM_INT = 1; // flag that it's already setup for direct control
|
422
|
424
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ISR_table[i].PWM_mask = 0;
|
423
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- ISR_table[i].PCR_bit = map_MR[j].PCR_bit; // PCR register bit to enable PWM1 control of this pin
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424
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- ISR_table[i].PINSEL_reg = map_MR[j].PINSEL_reg; // PINSEL register address to set pin mode to PWM1 control} MR_map;
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425
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- ISR_table[i].PINSEL_bits = map_MR[j].PINSEL_bits; // PINSEL register bits to set pin mode to PWM1 control} MR_map;
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425
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+ ISR_table[i].PCR_bit = map_MR[j].PCR_bit; // PCR register bit to enable PWM1 control of this pin
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426
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+ ISR_table[i].PINSEL_reg = map_MR[j].PINSEL_reg; // PINSEL register address to set pin mode to PWM1 control} MR_map;
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427
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+ ISR_table[i].PINSEL_bits = map_MR[j].PINSEL_bits; // PINSEL register bits to set pin mode to PWM1 control} MR_map;
|
426
|
428
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map_MR[j].map_used = 2;
|
427
|
429
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ISR_table[i].PWM_flag = 0;
|
428
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430
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*map_MR[j].MR_register = ISR_table[i].microseconds;
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