[2.0.x] LPC1768 upload_extra_script.py fix (wrong type of exit method)

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

* Use a different method to find the volume info in Windows

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

- Ordering and match classification between `boards.h` and `pins.h`
- Check `pins.h` environments

STM32 ARM Cortex-M3 boards were listed as M4

Fix #10777 for 2.0.x

Co-Authored-By: Ante Vukorepa <o.orcinus@gmail.com>

As noted in #10777

Fix #10761

[2.0.x] Refactor, optimization of core planner/stepper/endstops logic

- Also implemented real endstop reading on interrupt.

- Fixed the planner incorrectly avoiding optimization of the block following the active one.
- Added extra conditions to terminate planner early and avoid redundant computations.

Allows the Stepper ISR to wait until a given block is free for use. Allows Planner to plan the first move, which is split into two.

Better encapsulation and considerably reduce stepper jitter

Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

Alternative to the apparently superfluous double delay

Followup to #10656