My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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SPI.cpp 27KB

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  1. /******************************************************************************
  2. * The MIT License
  3. *
  4. * Copyright (c) 2010 Perry Hung.
  5. *
  6. * Permission is hereby granted, free of charge, to any person
  7. * obtaining a copy of this software and associated documentation
  8. * files (the "Software"), to deal in the Software without
  9. * restriction, including without limitation the rights to use, copy,
  10. * modify, merge, publish, distribute, sublicense, and/or sell copies
  11. * of the Software, and to permit persons to whom the Software is
  12. * furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be
  15. * included in all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  20. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  21. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  22. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  23. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  24. * SOFTWARE.
  25. *****************************************************************************/
  26. /**
  27. * @author Marti Bolivar <mbolivar@leaflabs.com>
  28. * @brief Wirish SPI implementation.
  29. */
  30. #ifdef __STM32F1__
  31. #include "SPI.h"
  32. #include <libmaple/timer.h>
  33. #include <libmaple/util.h>
  34. #include <libmaple/rcc.h>
  35. #include <boards.h>
  36. #include <wirish.h>
  37. /** Time in ms for DMA receive timeout */
  38. #define DMA_TIMEOUT 100
  39. #if CYCLES_PER_MICROSECOND != 72
  40. #warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
  41. #endif
  42. struct spi_pins {
  43. uint8_t nss;
  44. uint8_t sck;
  45. uint8_t miso;
  46. uint8_t mosi;
  47. };
  48. static const spi_pins* dev_to_spi_pins(spi_dev *dev);
  49. static void configure_gpios(spi_dev *dev, bool as_master);
  50. static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq);
  51. #if (BOARD_NR_SPI >= 3) && !defined(STM32_HIGH_DENSITY)
  52. #error "The SPI library is misconfigured: 3 SPI ports only available on high density STM32 devices"
  53. #endif
  54. static const spi_pins board_spi_pins[] __FLASH__ = {
  55. #if BOARD_NR_SPI >= 1
  56. { BOARD_SPI1_NSS_PIN,
  57. BOARD_SPI1_SCK_PIN,
  58. BOARD_SPI1_MISO_PIN,
  59. BOARD_SPI1_MOSI_PIN },
  60. #endif
  61. #if BOARD_NR_SPI >= 2
  62. { BOARD_SPI2_NSS_PIN,
  63. BOARD_SPI2_SCK_PIN,
  64. BOARD_SPI2_MISO_PIN,
  65. BOARD_SPI2_MOSI_PIN },
  66. #endif
  67. #if BOARD_NR_SPI >= 3
  68. { BOARD_SPI3_NSS_PIN,
  69. BOARD_SPI3_SCK_PIN,
  70. BOARD_SPI3_MISO_PIN,
  71. BOARD_SPI3_MOSI_PIN },
  72. #endif
  73. };
  74. #if BOARD_NR_SPI >= 1
  75. static void (*_spi1_this);
  76. #endif
  77. #if BOARD_NR_SPI >= 2
  78. static void (*_spi2_this);
  79. #endif
  80. #if BOARD_NR_SPI >= 3
  81. static void (*_spi3_this);
  82. #endif
  83. /**
  84. * Constructor
  85. */
  86. SPIClass::SPIClass(uint32_t spi_num) {
  87. _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
  88. switch (spi_num) {
  89. #if BOARD_NR_SPI >= 1
  90. case 1:
  91. _currentSetting->spi_d = SPI1;
  92. _spi1_this = (void*)this;
  93. break;
  94. #endif
  95. #if BOARD_NR_SPI >= 2
  96. case 2:
  97. _currentSetting->spi_d = SPI2;
  98. _spi2_this = (void*)this;
  99. break;
  100. #endif
  101. #if BOARD_NR_SPI >= 3
  102. case 3:
  103. _currentSetting->spi_d = SPI3;
  104. _spi3_this = (void*)this;
  105. break;
  106. #endif
  107. default: ASSERT(0);
  108. }
  109. // Init things specific to each SPI device
  110. // clock divider setup is a bit of hack, and needs to be improved at a later date.
  111. #if BOARD_NR_SPI >= 1
  112. _settings[0].spi_d = SPI1;
  113. _settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock);
  114. _settings[0].spiDmaDev = DMA1;
  115. _settings[0].spiTxDmaChannel = DMA_CH3;
  116. _settings[0].spiRxDmaChannel = DMA_CH2;
  117. #endif
  118. #if BOARD_NR_SPI >= 2
  119. _settings[1].spi_d = SPI2;
  120. _settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock);
  121. _settings[1].spiDmaDev = DMA1;
  122. _settings[1].spiTxDmaChannel = DMA_CH5;
  123. _settings[1].spiRxDmaChannel = DMA_CH4;
  124. #endif
  125. #if BOARD_NR_SPI >= 3
  126. _settings[2].spi_d = SPI3;
  127. _settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock);
  128. _settings[2].spiDmaDev = DMA2;
  129. _settings[2].spiTxDmaChannel = DMA_CH2;
  130. _settings[2].spiRxDmaChannel = DMA_CH1;
  131. #endif
  132. // added for DMA callbacks.
  133. _currentSetting->state = SPI_STATE_IDLE;
  134. }
  135. /*
  136. * Set up/tear down
  137. */
  138. void SPIClass::updateSettings() {
  139. uint32_t flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS);
  140. spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
  141. }
  142. void SPIClass::begin() {
  143. spi_init(_currentSetting->spi_d);
  144. configure_gpios(_currentSetting->spi_d, 1);
  145. updateSettings();
  146. // added for DMA callbacks.
  147. _currentSetting->state = SPI_STATE_READY;
  148. }
  149. void SPIClass::beginSlave() {
  150. spi_init(_currentSetting->spi_d);
  151. configure_gpios(_currentSetting->spi_d, 0);
  152. uint32_t flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize);
  153. spi_slave_enable(_currentSetting->spi_d, (spi_mode)_currentSetting->dataMode, flags);
  154. // added for DMA callbacks.
  155. _currentSetting->state = SPI_STATE_READY;
  156. }
  157. void SPIClass::end() {
  158. if (!spi_is_enabled(_currentSetting->spi_d))
  159. return;
  160. // Follows RM0008's sequence for disabling a SPI in master/slave
  161. // full duplex mode.
  162. while (spi_is_rx_nonempty(_currentSetting->spi_d)) {
  163. // FIXME [0.1.0] remove this once you have an interrupt based driver
  164. volatile uint16_t rx __attribute__((unused)) = spi_rx_reg(_currentSetting->spi_d);
  165. }
  166. while (!spi_is_tx_empty(_currentSetting->spi_d)) {};
  167. while (spi_is_busy(_currentSetting->spi_d)) {};
  168. spi_peripheral_disable(_currentSetting->spi_d);
  169. // added for DMA callbacks.
  170. // Need to add unsetting the callbacks for the DMA channels.
  171. _currentSetting->state = SPI_STATE_IDLE;
  172. }
  173. /* Roger Clark added 3 functions */
  174. void SPIClass::setClockDivider(uint32_t clockDivider) {
  175. _currentSetting->clockDivider = clockDivider;
  176. uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR);
  177. _currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR);
  178. }
  179. void SPIClass::setBitOrder(BitOrder bitOrder) {
  180. _currentSetting->bitOrder = bitOrder;
  181. uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST);
  182. if (bitOrder == LSBFIRST) cr1 |= SPI_CR1_LSBFIRST;
  183. _currentSetting->spi_d->regs->CR1 = cr1;
  184. }
  185. /* Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
  186. * Input parameter should be SPI_CR1_DFF set to 0 or 1 on a 32bit word.
  187. *
  188. */
  189. void SPIClass::setDataSize(uint32_t datasize) {
  190. _currentSetting->dataSize = datasize;
  191. uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
  192. uint8_t en = spi_is_enabled(_currentSetting->spi_d);
  193. spi_peripheral_disable(_currentSetting->spi_d);
  194. _currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en;
  195. }
  196. void SPIClass::setDataMode(uint8_t dataMode) {
  197. /* Notes:
  198. As far as I can tell, the AVR numbers for dataMode appear to match the numbers required by the STM32
  199. From the AVR doc http://www.atmel.com/images/doc2585.pdf section 2.4
  200. SPI Mode CPOL CPHA Shift SCK-edge Capture SCK-edge
  201. 0 0 0 Falling Rising
  202. 1 0 1 Rising Falling
  203. 2 1 0 Rising Falling
  204. 3 1 1 Falling Rising
  205. On the STM32 it appears to be
  206. bit 1 - CPOL : Clock polarity
  207. (This bit should not be changed when communication is ongoing)
  208. 0 : CLK to 0 when idle
  209. 1 : CLK to 1 when idle
  210. bit 0 - CPHA : Clock phase
  211. (This bit should not be changed when communication is ongoing)
  212. 0 : The first clock transition is the first data capture edge
  213. 1 : The second clock transition is the first data capture edge
  214. If someone finds this is not the case or sees a logic error with this let me know ;-)
  215. */
  216. _currentSetting->dataMode = dataMode;
  217. uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA);
  218. _currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA));
  219. }
  220. void SPIClass::beginTransaction(uint8_t pin, SPISettings settings) {
  221. setBitOrder(settings.bitOrder);
  222. setDataMode(settings.dataMode);
  223. setDataSize(settings.dataSize);
  224. setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
  225. begin();
  226. }
  227. void SPIClass::beginTransactionSlave(SPISettings settings) {
  228. setBitOrder(settings.bitOrder);
  229. setDataMode(settings.dataMode);
  230. setDataSize(settings.dataSize);
  231. beginSlave();
  232. }
  233. void SPIClass::endTransaction() { }
  234. /*
  235. * I/O
  236. */
  237. uint16_t SPIClass::read() {
  238. while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
  239. return (uint16)spi_rx_reg(_currentSetting->spi_d);
  240. }
  241. void SPIClass::read(uint8_t *buf, uint32_t len) {
  242. if (len == 0) return;
  243. spi_rx_reg(_currentSetting->spi_d); // clear the RX buffer in case a byte is waiting on it.
  244. spi_reg_map * regs = _currentSetting->spi_d->regs;
  245. // start sequence: write byte 0
  246. regs->DR = 0x00FF; // write the first byte
  247. // main loop
  248. while ( (--len) ) {
  249. while( !(regs->SR & SPI_SR_TXE) ); // wait for TXE flag
  250. noInterrupts(); // go atomic level - avoid interrupts to surely get the previously received data
  251. regs->DR = 0x00FF; // write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
  252. while ( !(regs->SR & SPI_SR_RXNE) ); // wait till data is available in the DR register
  253. *buf++ = (uint8)(regs->DR); // read and store the received byte. This clears the RXNE flag.
  254. interrupts(); // let systick do its job
  255. }
  256. // read remaining last byte
  257. while ( !(regs->SR & SPI_SR_RXNE) ) {} // wait till data is available in the Rx register
  258. *buf++ = (uint8)(regs->DR); // read and store the received byte
  259. }
  260. void SPIClass::write(uint16_t data) {
  261. /* Added for 16bit data Victor Perez. Roger Clark
  262. * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
  263. * by taking the Tx code from transfer(byte)
  264. * This almost doubles the speed of this function.
  265. */
  266. spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
  267. while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
  268. while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
  269. }
  270. void SPIClass::write16(uint16_t data) {
  271. // Added by stevestrong: write two consecutive bytes in 8 bit mode (DFF=0)
  272. spi_tx_reg(_currentSetting->spi_d, data>>8); // write high byte
  273. while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1
  274. spi_tx_reg(_currentSetting->spi_d, data); // write low byte
  275. while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1
  276. while (spi_is_busy(_currentSetting->spi_d) != 0); // wait until BSY=0
  277. }
  278. void SPIClass::write(uint16_t data, uint32_t n) {
  279. // Added by stevstrong: Repeatedly send same data by the specified number of times
  280. spi_reg_map * regs = _currentSetting->spi_d->regs;
  281. while ( (n--)>0 ) {
  282. regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
  283. while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
  284. }
  285. while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning
  286. }
  287. void SPIClass::write(const void *data, uint32_t length) {
  288. spi_dev * spi_d = _currentSetting->spi_d;
  289. spi_tx(spi_d, data, length); // data can be array of bytes or words
  290. while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
  291. while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
  292. }
  293. uint8_t SPIClass::transfer(uint8_t byte) const {
  294. spi_dev * spi_d = _currentSetting->spi_d;
  295. spi_rx_reg(spi_d); // read any previous data
  296. spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
  297. while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
  298. while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
  299. return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
  300. }
  301. uint16_t SPIClass::transfer16(uint16_t data) const {
  302. // Modified by stevestrong: write & read two consecutive bytes in 8 bit mode (DFF=0)
  303. // This is more effective than two distinct byte transfers
  304. spi_dev * spi_d = _currentSetting->spi_d;
  305. spi_rx_reg(spi_d); // read any previous data
  306. spi_tx_reg(spi_d, data>>8); // write high byte
  307. while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1
  308. while (spi_is_busy(spi_d) != 0); // wait until BSY=0
  309. uint16_t ret = spi_rx_reg(spi_d)<<8; // read and shift high byte
  310. spi_tx_reg(spi_d, data); // write low byte
  311. while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1
  312. while (spi_is_busy(spi_d) != 0); // wait until BSY=0
  313. ret += spi_rx_reg(spi_d); // read low byte
  314. return ret;
  315. }
  316. /* Roger Clark and Victor Perez, 2015
  317. * Performs a DMA SPI transfer with at least a receive buffer.
  318. * If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer.
  319. * On exit TX buffer is not modified, and RX buffer cotains the received data.
  320. * Still in progress.
  321. */
  322. void SPIClass::dmaTransferSet(const void *transmitBuf, void *receiveBuf) {
  323. dma_init(_currentSetting->spiDmaDev);
  324. //spi_rx_dma_enable(_currentSetting->spi_d);
  325. //spi_tx_dma_enable(_currentSetting->spi_d);
  326. dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
  327. dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR,
  328. dma_bit_size, receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT ));// receive buffer DMA
  329. if (!transmitBuf) {
  330. transmitBuf = &ff;
  331. dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR,
  332. dma_bit_size, (volatile void*)transmitBuf, dma_bit_size, (DMA_FROM_MEM));// Transmit FF repeatedly
  333. }
  334. else {
  335. dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR,
  336. dma_bit_size, (volatile void*)transmitBuf, dma_bit_size, (DMA_MINC_MODE | DMA_FROM_MEM ));// Transmit buffer DMA
  337. }
  338. dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
  339. dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, DMA_PRIORITY_VERY_HIGH);
  340. }
  341. uint8_t SPIClass::dmaTransferRepeat(uint16_t length) {
  342. if (length == 0) return 0;
  343. if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) spi_rx_reg(_currentSetting->spi_d);
  344. _currentSetting->state = SPI_STATE_TRANSFER;
  345. dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
  346. dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
  347. dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
  348. dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
  349. spi_rx_dma_enable(_currentSetting->spi_d);
  350. spi_tx_dma_enable(_currentSetting->spi_d);
  351. if (_currentSetting->receiveCallback)
  352. return 0;
  353. //uint32_t m = millis();
  354. uint8_t b = 0;
  355. uint32_t m = millis();
  356. while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1) == 0) {
  357. //Avoid interrupts and just loop waiting for the flag to be set.
  358. if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
  359. }
  360. while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
  361. while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
  362. spi_tx_dma_disable(_currentSetting->spi_d);
  363. spi_rx_dma_disable(_currentSetting->spi_d);
  364. dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
  365. dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
  366. dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
  367. dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
  368. _currentSetting->state = SPI_STATE_READY;
  369. return b;
  370. }
  371. /* Roger Clark and Victor Perez, 2015
  372. * Performs a DMA SPI transfer with at least a receive buffer.
  373. * If a TX buffer is not provided, FF is sent over and over for the length of the transfer.
  374. * On exit TX buffer is not modified, and RX buffer contains the received data.
  375. * Still in progress.
  376. */
  377. uint8_t SPIClass::dmaTransfer(const void *transmitBuf, void *receiveBuf, uint16_t length) {
  378. dmaTransferSet(transmitBuf, receiveBuf);
  379. return dmaTransferRepeat(length);
  380. }
  381. /* Roger Clark and Victor Perez, 2015
  382. * Performs a DMA SPI send using a TX buffer.
  383. * On exit TX buffer is not modified.
  384. * Still in progress.
  385. * 2016 - stevstrong - reworked to automatically detect bit size from SPI setting
  386. */
  387. void SPIClass::dmaSendSet(const void * transmitBuf, bool minc) {
  388. uint32_t flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
  389. dma_init(_currentSetting->spiDmaDev);
  390. dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
  391. dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
  392. (volatile void*)transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
  393. dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
  394. }
  395. uint8_t SPIClass::dmaSendRepeat(uint16_t length) {
  396. if (length == 0) return 0;
  397. dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
  398. dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
  399. _currentSetting->state = SPI_STATE_TRANSMIT;
  400. dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
  401. spi_tx_dma_enable(_currentSetting->spi_d);
  402. if (_currentSetting->transmitCallback)
  403. return 0;
  404. uint32_t m = millis();
  405. uint8_t b = 0;
  406. while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
  407. //Avoid interrupts and just loop waiting for the flag to be set.
  408. if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
  409. }
  410. while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
  411. while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
  412. spi_tx_dma_disable(_currentSetting->spi_d);
  413. dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
  414. dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
  415. _currentSetting->state = SPI_STATE_READY;
  416. return b;
  417. }
  418. uint8_t SPIClass::dmaSend(const void * transmitBuf, uint16_t length, bool minc) {
  419. dmaSendSet(transmitBuf, minc);
  420. return dmaSendRepeat(length);
  421. }
  422. uint8_t SPIClass::dmaSendAsync(const void * transmitBuf, uint16_t length, bool minc) {
  423. uint8_t b = 0;
  424. if (_currentSetting->state != SPI_STATE_READY) {
  425. uint32_t m = millis();
  426. while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
  427. //Avoid interrupts and just loop waiting for the flag to be set.
  428. //delayMicroseconds(10);
  429. if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
  430. }
  431. while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
  432. while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
  433. spi_tx_dma_disable(_currentSetting->spi_d);
  434. dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
  435. _currentSetting->state = SPI_STATE_READY;
  436. }
  437. if (length == 0) return 0;
  438. uint32_t flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
  439. dma_init(_currentSetting->spiDmaDev);
  440. // TX
  441. dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
  442. dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR,
  443. dma_bit_size, (volatile void*)transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
  444. dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
  445. dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
  446. dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
  447. spi_tx_dma_enable(_currentSetting->spi_d);
  448. _currentSetting->state = SPI_STATE_TRANSMIT;
  449. return b;
  450. }
  451. /**
  452. * New functions added to manage callbacks.
  453. * Victor Perez 2017
  454. */
  455. void SPIClass::onReceive(void(*callback)(void)) {
  456. _currentSetting->receiveCallback = callback;
  457. if (callback) {
  458. switch (_currentSetting->spi_d->clk_id) {
  459. #if BOARD_NR_SPI >= 1
  460. case RCC_SPI1:
  461. dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi1EventCallback);
  462. break;
  463. #endif
  464. #if BOARD_NR_SPI >= 2
  465. case RCC_SPI2:
  466. dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi2EventCallback);
  467. break;
  468. #endif
  469. #if BOARD_NR_SPI >= 3
  470. case RCC_SPI3:
  471. dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi3EventCallback);
  472. break;
  473. #endif
  474. default:
  475. ASSERT(0);
  476. }
  477. }
  478. else {
  479. dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
  480. }
  481. }
  482. void SPIClass::onTransmit(void(*callback)(void)) {
  483. _currentSetting->transmitCallback = callback;
  484. if (callback) {
  485. switch (_currentSetting->spi_d->clk_id) {
  486. #if BOARD_NR_SPI >= 1
  487. case RCC_SPI1:
  488. dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi1EventCallback);
  489. break;
  490. #endif
  491. #if BOARD_NR_SPI >= 2
  492. case RCC_SPI2:
  493. dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi2EventCallback);
  494. break;
  495. #endif
  496. #if BOARD_NR_SPI >= 3
  497. case RCC_SPI3:
  498. dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi3EventCallback);
  499. break;
  500. #endif
  501. default:
  502. ASSERT(0);
  503. }
  504. }
  505. else {
  506. dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
  507. }
  508. }
  509. /**
  510. * TODO: check if better to first call the customer code, next disable the DMA requests.
  511. * Also see if we need to check whether callbacks are set or not, may be better to be checked
  512. * during the initial setup and only set the callback to EventCallback if they are set.
  513. */
  514. void SPIClass::EventCallback() {
  515. while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
  516. while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0"
  517. switch (_currentSetting->state) {
  518. case SPI_STATE_TRANSFER:
  519. while (spi_is_rx_nonempty(_currentSetting->spi_d));
  520. _currentSetting->state = SPI_STATE_READY;
  521. spi_tx_dma_disable(_currentSetting->spi_d);
  522. spi_rx_dma_disable(_currentSetting->spi_d);
  523. //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
  524. //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
  525. if (_currentSetting->receiveCallback)
  526. _currentSetting->receiveCallback();
  527. break;
  528. case SPI_STATE_TRANSMIT:
  529. _currentSetting->state = SPI_STATE_READY;
  530. spi_tx_dma_disable(_currentSetting->spi_d);
  531. //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
  532. if (_currentSetting->transmitCallback)
  533. _currentSetting->transmitCallback();
  534. break;
  535. default:
  536. break;
  537. }
  538. }
  539. void SPIClass::attachInterrupt() {
  540. // Should be enableInterrupt()
  541. }
  542. void SPIClass::detachInterrupt() {
  543. // Should be disableInterrupt()
  544. }
  545. /*
  546. * Pin accessors
  547. */
  548. uint8_t SPIClass::misoPin() {
  549. return dev_to_spi_pins(_currentSetting->spi_d)->miso;
  550. }
  551. uint8_t SPIClass::mosiPin() {
  552. return dev_to_spi_pins(_currentSetting->spi_d)->mosi;
  553. }
  554. uint8_t SPIClass::sckPin() {
  555. return dev_to_spi_pins(_currentSetting->spi_d)->sck;
  556. }
  557. uint8_t SPIClass::nssPin() {
  558. return dev_to_spi_pins(_currentSetting->spi_d)->nss;
  559. }
  560. /*
  561. * Deprecated functions
  562. */
  563. uint8_t SPIClass::send(uint8_t data) {
  564. this->write(data);
  565. return 1;
  566. }
  567. uint8_t SPIClass::send(uint8_t *buf, uint32_t len) {
  568. this->write(buf, len);
  569. return len;
  570. }
  571. uint8_t SPIClass::recv() {
  572. return this->read();
  573. }
  574. /*
  575. * DMA call back functions, one per port.
  576. */
  577. #if BOARD_NR_SPI >= 1
  578. void SPIClass::_spi1EventCallback() {
  579. reinterpret_cast<class SPIClass*>(_spi1_this)->EventCallback();
  580. }
  581. #endif
  582. #if BOARD_NR_SPI >= 2
  583. void SPIClass::_spi2EventCallback() {
  584. reinterpret_cast<class SPIClass*>(_spi2_this)->EventCallback();
  585. }
  586. #endif
  587. #if BOARD_NR_SPI >= 3
  588. void SPIClass::_spi3EventCallback() {
  589. reinterpret_cast<class SPIClass*>(_spi3_this)->EventCallback();
  590. }
  591. #endif
  592. /*
  593. * Auxiliary functions
  594. */
  595. static const spi_pins* dev_to_spi_pins(spi_dev *dev) {
  596. switch (dev->clk_id) {
  597. #if BOARD_NR_SPI >= 1
  598. case RCC_SPI1: return board_spi_pins;
  599. #endif
  600. #if BOARD_NR_SPI >= 2
  601. case RCC_SPI2: return board_spi_pins + 1;
  602. #endif
  603. #if BOARD_NR_SPI >= 3
  604. case RCC_SPI3: return board_spi_pins + 2;
  605. #endif
  606. default: return NULL;
  607. }
  608. }
  609. static void disable_pwm(const stm32_pin_info *i) {
  610. if (i->timer_device)
  611. timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
  612. }
  613. static void configure_gpios(spi_dev *dev, bool as_master) {
  614. const spi_pins *pins = dev_to_spi_pins(dev);
  615. if (!pins) return;
  616. const stm32_pin_info *nssi = &PIN_MAP[pins->nss],
  617. *scki = &PIN_MAP[pins->sck],
  618. *misoi = &PIN_MAP[pins->miso],
  619. *mosii = &PIN_MAP[pins->mosi];
  620. disable_pwm(nssi);
  621. disable_pwm(scki);
  622. disable_pwm(misoi);
  623. disable_pwm(mosii);
  624. spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
  625. scki->gpio_device, scki->gpio_bit, misoi->gpio_bit,
  626. mosii->gpio_bit);
  627. }
  628. static const spi_baud_rate baud_rates[8] __FLASH__ = {
  629. SPI_BAUD_PCLK_DIV_2,
  630. SPI_BAUD_PCLK_DIV_4,
  631. SPI_BAUD_PCLK_DIV_8,
  632. SPI_BAUD_PCLK_DIV_16,
  633. SPI_BAUD_PCLK_DIV_32,
  634. SPI_BAUD_PCLK_DIV_64,
  635. SPI_BAUD_PCLK_DIV_128,
  636. SPI_BAUD_PCLK_DIV_256,
  637. };
  638. /*
  639. * Note: This assumes you're on a LeafLabs-style board
  640. * (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
  641. */
  642. static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
  643. uint32_t clock = 0;
  644. switch (rcc_dev_clk(dev->clk_id)) {
  645. case RCC_AHB:
  646. case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
  647. case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
  648. }
  649. clock >>= 1;
  650. uint8_t i = 0;
  651. while (i < 7 && freq < clock) { clock >>= 1; i++; }
  652. return baud_rates[i];
  653. }
  654. SPIClass SPI(1);
  655. #endif // __STM32F1__