Minor HAL cleanup

Marlin/src/HAL/DUE/dogm/u8g_com_HAL_DUE_shared_hw_spi.cpp

 
 #endif // HAS_GRAPHICAL_LCD
 
-#endif //__SAM3X8E__
+#endif // __SAM3X8E__

Marlin/src/HAL/STM32F1/SoftwareSerial.cpp

   listening = false;
 }
 
-#endif //__STM32F1__
+#endif // __STM32F1__

Marlin/src/HAL/STM32_F4_F7/HAL_SPI.cpp

  */
 void spiBegin() {
   #if !defined(SS_PIN) || SS_PIN < 0
-    #error SS_PIN not defined!
+    #error "SS_PIN not defined!"
   #endif
 
   OUT_WRITE(SS_PIN, HIGH);

Marlin/src/HAL/TEENSY31_32/HAL.h

 //#undef MOTHERBOARD
 //#define MOTHERBOARD BOARD_TEENSY31_32
 
-#define IS_32BIT_TEENSY defined(__MK20DX256__)
-#define IS_TEENSY32 defined(__MK20DX256__)
+#ifdef __MK20DX256__
+  #define IS_32BIT_TEENSY 1
+  #define IS_TEENSY32 1
+#endif
 
 #define NUM_SERIAL 1
 

Marlin/src/HAL/TEENSY35_36/HAL.h

 // Defines
 // ------------------------
 
-#define IS_32BIT_TEENSY (defined(__MK64FX512__) || defined(__MK66FX1M0__))
-#define IS_TEENSY35 defined(__MK64FX512__)
-#define IS_TEENSY36 defined(__MK66FX1M0__)
+#ifdef __MK64FX512__
+  #define IS_32BIT_TEENSY 1
+  #define IS_TEENSY35 1
+#endif
+#ifdef __MK66FX1M0__
+  #define IS_32BIT_TEENSY 1
+  #define IS_TEENSY36 1
+#endif
 
 #define NUM_SERIAL 1
 

Marlin/src/HAL/TEENSY35_36/HAL_SPI.cpp

 
 void spiBegin() {
   #if !PIN_EXISTS(SS)
-    #error SS_PIN not defined!
+    #error "SS_PIN not defined!"
   #endif
   OUT_WRITE(SS_PIN, HIGH);
   SET_OUTPUT(SCK_PIN);

Marlin/src/HAL/shared/backtrace/unwmemaccess.cpp

 /* Validate address */
 
 #ifdef ARDUINO_ARCH_SAM
-// For DUE, valid address ranges are
-//  SRAM  (0x20070000 - 0x20088000) (96kb)
-//  FLASH (0x00080000 - 0x00100000) (512kb)
-//
-#define START_SRAM_ADDR   0x20070000
-#define END_SRAM_ADDR     0x20088000
-#define START_FLASH_ADDR  0x00080000
-#define END_FLASH_ADDR    0x00100000
-#endif
-
-#ifdef TARGET_LPC1768
-// For LPC1769:
-//  SRAM  (0x10000000 - 0x10008000) (32kb)
-//  FLASH (0x00000000 - 0x00080000) (512kb)
-//
-#define START_SRAM_ADDR   0x10000000
-#define END_SRAM_ADDR     0x10008000
-#define START_FLASH_ADDR  0x00000000
-#define END_FLASH_ADDR    0x00080000
-#endif
-
-#if 0
-// For STM32F103CBT6
-//  SRAM  (0x20000000 - 0x20005000) (20kb)
-//  FLASH (0x00000000 - 0x00020000) (128kb)
-//
-#define START_SRAM_ADDR   0x20000000
-#define END_SRAM_ADDR     0x20005000
-#define START_FLASH_ADDR  0x00000000
-#define END_FLASH_ADDR    0x00020000
-#endif
 
-#if defined(__STM32F1__) || defined(STM32F1xx) || defined(STM32F0xx)
-// For STM32F103ZET6/STM32F103VET6/STM32F0xx
-//  SRAM  (0x20000000 - 0x20010000) (64kb)
-//  FLASH (0x00000000 - 0x00080000) (512kb)
-//
-#define START_SRAM_ADDR   0x20000000
-#define END_SRAM_ADDR     0x20010000
-#define START_FLASH_ADDR  0x00000000
-#define END_FLASH_ADDR    0x00080000
-#endif
-
-#if defined(STM32F4) || defined(STM32F4xx)
-// For STM32F407VET
-//  SRAM  (0x20000000 - 0x20030000) (192kb)
-//  FLASH (0x08000000 - 0x08080000) (512kb)
-//
-#define START_SRAM_ADDR   0x20000000
-#define END_SRAM_ADDR     0x20030000
-#define START_FLASH_ADDR  0x08000000
-#define END_FLASH_ADDR    0x08080000
-#endif
-
-#if MB(THE_BORG)
-// For STM32F765 in BORG
-//  SRAM  (0x20000000 - 0x20080000) (512kb)
-//  FLASH (0x08000000 - 0x08100000) (1024kb)
-//
-#define START_SRAM_ADDR   0x20000000
-#define END_SRAM_ADDR     0x20080000
-#define START_FLASH_ADDR  0x08000000
-#define END_FLASH_ADDR    0x08100000
-#endif
+  // For DUE, valid address ranges are
+  //  SRAM  (0x20070000 - 0x20088000) (96kb)
+  //  FLASH (0x00080000 - 0x00100000) (512kb)
+  //
+  #define START_SRAM_ADDR   0x20070000
+  #define END_SRAM_ADDR     0x20088000
+  #define START_FLASH_ADDR  0x00080000
+  #define END_FLASH_ADDR    0x00100000
+
+#elif defined(TARGET_LPC1768)
+
+  // For LPC1769:
+  //  SRAM  (0x10000000 - 0x10008000) (32kb)
+  //  FLASH (0x00000000 - 0x00080000) (512kb)
+  //
+  #define START_SRAM_ADDR   0x10000000
+  #define END_SRAM_ADDR     0x10008000
+  #define START_FLASH_ADDR  0x00000000
+  #define END_FLASH_ADDR    0x00080000
+
+#elif 0
+
+  // For STM32F103CBT6
+  //  SRAM  (0x20000000 - 0x20005000) (20kb)
+  //  FLASH (0x00000000 - 0x00020000) (128kb)
+  //
+  #define START_SRAM_ADDR   0x20000000
+  #define END_SRAM_ADDR     0x20005000
+  #define START_FLASH_ADDR  0x00000000
+  #define END_FLASH_ADDR    0x00020000
+
+#elif defined(__STM32F1__) || defined(STM32F1xx) || defined(STM32F0xx)
+
+  // For STM32F103ZET6/STM32F103VET6/STM32F0xx
+  //  SRAM  (0x20000000 - 0x20010000) (64kb)
+  //  FLASH (0x00000000 - 0x00080000) (512kb)
+  //
+  #define START_SRAM_ADDR   0x20000000
+  #define END_SRAM_ADDR     0x20010000
+  #define START_FLASH_ADDR  0x00000000
+  #define END_FLASH_ADDR    0x00080000
+
+#elif defined(STM32F4) || defined(STM32F4xx)
+
+  // For STM32F407VET
+  //  SRAM  (0x20000000 - 0x20030000) (192kb)
+  //  FLASH (0x08000000 - 0x08080000) (512kb)
+  //
+  #define START_SRAM_ADDR   0x20000000
+  #define END_SRAM_ADDR     0x20030000
+  #define START_FLASH_ADDR  0x08000000
+  #define END_FLASH_ADDR    0x08080000
+
+#elif MB(THE_BORG)
+
+  // For STM32F765 in BORG
+  //  SRAM  (0x20000000 - 0x20080000) (512kb)
+  //  FLASH (0x08000000 - 0x08100000) (1024kb)
+  //
+  #define START_SRAM_ADDR   0x20000000
+  #define END_SRAM_ADDR     0x20080000
+  #define START_FLASH_ADDR  0x08000000
+  #define END_FLASH_ADDR    0x08100000
+
+#elif MB(REMRAM_V1)
+
+  // For STM32F765VI in RemRam v1
+  //  SRAM  (0x20000000 - 0x20080000) (512kb)
+  //  FLASH (0x08000000 - 0x08200000) (2048kb)
+  //
+  #define START_SRAM_ADDR   0x20000000
+  #define END_SRAM_ADDR     0x20080000
+  #define START_FLASH_ADDR  0x08000000
+  #define END_FLASH_ADDR    0x08200000
+
+#elif defined(__MK20DX256__)
+
+  // For MK20DX256 in TEENSY 3.1 or TEENSY 3.2
+  //  SRAM  (0x1FFF8000 - 0x20008000) (64kb)
+  //  FLASH (0x00000000 - 0x00040000) (256kb)
+  //
+  #define START_SRAM_ADDR   0x1FFF8000
+  #define END_SRAM_ADDR     0x20008000
+  #define START_FLASH_ADDR  0x00000000
+  #define END_FLASH_ADDR    0x00040000
+
+#elif defined(__MK64FX512__)
+
+  // For MK64FX512 in TEENSY 3.5
+  //  SRAM  (0x1FFF0000 - 0x20020000) (192kb)
+  //  FLASH (0x00000000 - 0x00080000) (512kb)
+  //
+  #define START_SRAM_ADDR   0x1FFF0000
+  #define END_SRAM_ADDR     0x20020000
+  #define START_FLASH_ADDR  0x00000000
+  #define END_FLASH_ADDR    0x00080000
+
+#elif defined(__MK66FX1M0__)
+
+  // For MK66FX1M0 in TEENSY 3.6
+  //  SRAM  (0x1FFF0000 - 0x20030000) (256kb)
+  //  FLASH (0x00000000 - 0x00140000) (1.25Mb)
+  //
+  #define START_SRAM_ADDR   0x1FFF0000
+  #define END_SRAM_ADDR     0x20030000
+  #define START_FLASH_ADDR  0x00000000
+  #define END_FLASH_ADDR    0x00140000
+
+#elif defined(__SAMD51P20A__)
+
+  // For SAMD51x20, valid address ranges are
+  //  SRAM  (0x20000000 - 0x20040000) (256kb)
+  //  FLASH (0x00000000 - 0x00100000) (1024kb)
+  //
+  #define START_SRAM_ADDR   0x20000000
+  #define END_SRAM_ADDR     0x20040000
+  #define START_FLASH_ADDR  0x00000000
+  #define END_FLASH_ADDR    0x00100000
 
-#if MB(REMRAM_V1)
-// For STM32F765VI in RemRam v1
-//  SRAM  (0x20000000 - 0x20080000) (512kb)
-//  FLASH (0x08000000 - 0x08200000) (2048kb)
-//
-#define START_SRAM_ADDR   0x20000000
-#define END_SRAM_ADDR     0x20080000
-#define START_FLASH_ADDR  0x08000000
-#define END_FLASH_ADDR    0x08200000
-#endif
-
-#ifdef __MK20DX256__
-// For MK20DX256 in TEENSY 3.1 or TEENSY 3.2
-//  SRAM  (0x1FFF8000 - 0x20008000) (64kb)
-//  FLASH (0x00000000 - 0x00040000) (256kb)
-//
-#define START_SRAM_ADDR   0x1FFF8000
-#define END_SRAM_ADDR     0x20008000
-#define START_FLASH_ADDR  0x00000000
-#define END_FLASH_ADDR    0x00040000
-#endif
-
-#ifdef __MK64FX512__
-// For MK64FX512 in TEENSY 3.5
-//  SRAM  (0x1FFF0000 - 0x20020000) (192kb)
-//  FLASH (0x00000000 - 0x00080000) (512kb)
-//
-#define START_SRAM_ADDR   0x1FFF0000
-#define END_SRAM_ADDR     0x20020000
-#define START_FLASH_ADDR  0x00000000
-#define END_FLASH_ADDR    0x00080000
-#endif
-
-#ifdef __MK66FX1M0__
-// For MK66FX1M0 in TEENSY 3.6
-//  SRAM  (0x1FFF0000 - 0x20030000) (256kb)
-//  FLASH (0x00000000 - 0x00140000) (1.25Mb)
-//
-#define START_SRAM_ADDR   0x1FFF0000
-#define END_SRAM_ADDR     0x20030000
-#define START_FLASH_ADDR  0x00000000
-#define END_FLASH_ADDR    0x00140000
-#endif
-
-#ifdef __SAMD51P20A__
-// For SAMD51x20, valid address ranges are
-//  SRAM  (0x20000000 - 0x20040000) (256kb)
-//  FLASH (0x00000000 - 0x00100000) (1024kb)
-//
-#define START_SRAM_ADDR   0x20000000
-#define END_SRAM_ADDR     0x20040000
-#define START_FLASH_ADDR  0x00000000
-#define END_FLASH_ADDR    0x00100000
 #endif
 
 static bool validate_addr(uint32_t addr) {
   return true;
 }
 
-#endif
+#endif // __arm__ || __thumb__